1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * (C) Copyright 2008 3*4882a593Smuzhiyun * Mark Jonas <mark.jonas@de.bosch.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2007 6*4882a593Smuzhiyun * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * board/mpr2/lowlevel_init.S 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun#include <asm/macro.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun .global lowlevel_init 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun .text 17*4882a593Smuzhiyun .align 2 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunlowlevel_init: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun/* 22*4882a593Smuzhiyun * Set frequency multipliers and dividers in FRQCR. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun write16 WTCSR_A, WTCSR_D 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun write16 WTCNT_A, WTCNT_D 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun write16 FRQCR_A, FRQCR_D 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun/* 31*4882a593Smuzhiyun * Setup CS0 (Flash). 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun write32 CS0BCR_A, CS0BCR_D 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun write32 CS0WCR_A, CS0WCR_D 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun/* 38*4882a593Smuzhiyun * Setup CS3 (SDRAM). 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun write32 CS3BCR_A, CS3BCR_D 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun write32 CS3WCR_A, CS3WCR_D 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun write32 SDCR_A, SDCR_D1 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun write32 RTCSR_A, RTCSR_D 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun write32 RTCNT_A, RTCNT_D 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun write32 RTCOR_A, RTCOR_D 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun write32 SDCR_A, SDCR_D2 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun mov.l SDMR3_A, r1 55*4882a593Smuzhiyun mov.l SDMR3_D, r0 56*4882a593Smuzhiyun add r0, r1 57*4882a593Smuzhiyun mov #0, r0 58*4882a593Smuzhiyun mov.w r0, @r1 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun rts 61*4882a593Smuzhiyun nop 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun .align 4 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun/* 66*4882a593Smuzhiyun * Configuration for MPR2 A.3 through A.7 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun/* 70*4882a593Smuzhiyun * PLL Settings 71*4882a593Smuzhiyun */ 72*4882a593SmuzhiyunFRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ 73*4882a593SmuzhiyunWTCNT_D: .word 0x5A00 /* start counting at zero */ 74*4882a593SmuzhiyunWTCSR_D: .word 0xA507 /* divide by 4096 */ 75*4882a593Smuzhiyun.align 2 76*4882a593Smuzhiyun/* 77*4882a593Smuzhiyun * Spansion S29GL256N11 @ 48 MHz 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun/* 1 idle cycle inserted, normal space, 16 bit */ 80*4882a593SmuzhiyunCS0BCR_D: .long 0x12490400 81*4882a593Smuzhiyun/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ 82*4882a593SmuzhiyunCS0WCR_D: .long 0x00000340 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun/* 85*4882a593Smuzhiyun * Samsung K4S511632B-UL75 @ 48 MHz 86*4882a593Smuzhiyun * Micron MT48LC32M16A2-75 @ 48 MHz 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ 89*4882a593SmuzhiyunCS3BCR_D: .long 0x10004400 90*4882a593Smuzhiyun/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ 91*4882a593SmuzhiyunCS3WCR_D: .long 0x00000091 92*4882a593Smuzhiyun/* no refresh, 13 rows, 10 cols, NO bank active mode */ 93*4882a593SmuzhiyunSDCR_D1: .long 0x00000012 94*4882a593SmuzhiyunSDCR_D2: .long 0x00000812 /* refresh */ 95*4882a593SmuzhiyunRTCSR_D: .long 0xA55A0008 /* 1/4, once */ 96*4882a593SmuzhiyunRTCNT_D: .long 0xA55A005D /* count 93 */ 97*4882a593SmuzhiyunRTCOR_D: .long 0xa55a005d /* count 93 */ 98*4882a593Smuzhiyun/* mode register CL2, burst read and SINGLE WRITE */ 99*4882a593SmuzhiyunSDMR3_D: .long 0x440 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun/* 102*4882a593Smuzhiyun * Registers 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun 105*4882a593SmuzhiyunFRQCR_A: .long 0xA415FF80 106*4882a593SmuzhiyunWTCNT_A: .long 0xA415FF84 107*4882a593SmuzhiyunWTCSR_A: .long 0xA415FF86 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun#define BSC_BASE 0xA4FD0000 110*4882a593SmuzhiyunCS0BCR_A: .long BSC_BASE + 0x04 111*4882a593SmuzhiyunCS3BCR_A: .long BSC_BASE + 0x0C 112*4882a593SmuzhiyunCS0WCR_A: .long BSC_BASE + 0x24 113*4882a593SmuzhiyunCS3WCR_A: .long BSC_BASE + 0x2C 114*4882a593SmuzhiyunSDCR_A: .long BSC_BASE + 0x44 115*4882a593SmuzhiyunRTCSR_A: .long BSC_BASE + 0x48 116*4882a593SmuzhiyunRTCNT_A: .long BSC_BASE + 0x4C 117*4882a593SmuzhiyunRTCOR_A: .long BSC_BASE + 0x50 118*4882a593SmuzhiyunSDMR3_A: .long BSC_BASE + 0x5000 119