1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2010 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <i2c.h>
10*4882a593Smuzhiyun #include <linux/libfdt.h>
11*4882a593Smuzhiyun #include <fdt_support.h>
12*4882a593Smuzhiyun #include <pci.h>
13*4882a593Smuzhiyun #include <mpc83xx.h>
14*4882a593Smuzhiyun #include <netdev.h>
15*4882a593Smuzhiyun #include <asm/io.h>
16*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
17*4882a593Smuzhiyun #include <asm/fsl_mpc83xx_serdes.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
20*4882a593Smuzhiyun
checkboard(void)21*4882a593Smuzhiyun int checkboard(void)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun printf("Board: MPC8308 P1M\n");
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun return 0;
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static struct pci_region pcie_regions_0[] = {
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
31*4882a593Smuzhiyun .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
32*4882a593Smuzhiyun .size = CONFIG_SYS_PCIE1_MEM_SIZE,
33*4882a593Smuzhiyun .flags = PCI_REGION_MEM,
34*4882a593Smuzhiyun },
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
37*4882a593Smuzhiyun .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
38*4882a593Smuzhiyun .size = CONFIG_SYS_PCIE1_IO_SIZE,
39*4882a593Smuzhiyun .flags = PCI_REGION_IO,
40*4882a593Smuzhiyun },
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
pci_init_board(void)43*4882a593Smuzhiyun void pci_init_board(void)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
46*4882a593Smuzhiyun sysconf83xx_t *sysconf = &immr->sysconf;
47*4882a593Smuzhiyun law83xx_t *pcie_law = sysconf->pcielaw;
48*4882a593Smuzhiyun struct pci_region *pcie_reg[] = { pcie_regions_0 };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
51*4882a593Smuzhiyun FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Deassert the resets in the control register */
54*4882a593Smuzhiyun out_be32(&sysconf->pecr1, 0xE0008000);
55*4882a593Smuzhiyun udelay(2000);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* Configure PCI Express Local Access Windows */
58*4882a593Smuzhiyun out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
59*4882a593Smuzhiyun out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun mpc83xx_pcie_init(1, pcie_reg);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)65*4882a593Smuzhiyun int ft_board_setup(void *blob, bd_t *bd)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun ft_cpu_setup(blob, bd);
68*4882a593Smuzhiyun fsl_fdt_fixup_dr_usb(blob, bd);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun #endif
73*4882a593Smuzhiyun
board_eth_init(bd_t * bis)74*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun int rv, num_if = 0;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* Initialize TSECs first */
79*4882a593Smuzhiyun rv = cpu_eth_init(bis);
80*4882a593Smuzhiyun if (rv >= 0)
81*4882a593Smuzhiyun num_if += rv;
82*4882a593Smuzhiyun else
83*4882a593Smuzhiyun printf("ERROR: failed to initialize TSECs.\n");
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun rv = pci_eth_init(bis);
86*4882a593Smuzhiyun if (rv >= 0)
87*4882a593Smuzhiyun num_if += rv;
88*4882a593Smuzhiyun else
89*4882a593Smuzhiyun printf("ERROR: failed to initialize PCI Ethernet.\n");
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return num_if;
92*4882a593Smuzhiyun }
93