1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2006 Micronas GmbH 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * Premium & Platinum register addresses/definitions seem to be 11*4882a593Smuzhiyun * identical, so we only need to use one file for both platforms. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef _REG_FWSRAM_H_ 15*4882a593Smuzhiyun #define _REG_FWSRAM_H_ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define FWSRAM_BASE 0x00030000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Relative offsets of the register adresses */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define FWSRAM_SR_ADDR_OFFSET_OFFS 0x00002000 22*4882a593Smuzhiyun #define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) 23*4882a593Smuzhiyun #define FWSRAM_TOP_BOOT_LOG_OFFS 0x00002004 24*4882a593Smuzhiyun #define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) 25*4882a593Smuzhiyun #define FWSRAM_TOP_ROM_KBIST_OFFS 0x00002008 26*4882a593Smuzhiyun #define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) 27*4882a593Smuzhiyun #define FWSRAM_TOP_CID1_H_OFFS 0x0000200C 28*4882a593Smuzhiyun #define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) 29*4882a593Smuzhiyun #define FWSRAM_TOP_CID1_L_OFFS 0x00002010 30*4882a593Smuzhiyun #define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) 31*4882a593Smuzhiyun #define FWSRAM_TOP_CID2_H_OFFS 0x00002014 32*4882a593Smuzhiyun #define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) 33*4882a593Smuzhiyun #define FWSRAM_TOP_CID2_L_OFFS 0x00002018 34*4882a593Smuzhiyun #define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) 35*4882a593Smuzhiyun #define FWSRAM_TOP_TDO_CFG_OFFS 0x0000203C 36*4882a593Smuzhiyun #define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) 37*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_0_CFG_OFFS 0x00002040 38*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS) 39*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_1_CFG_OFFS 0x00002044 40*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS) 41*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_2_CFG_OFFS 0x00002048 42*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_2_CFG(base) ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS) 43*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_3_CFG_OFFS 0x0000204C 44*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_3_CFG(base) ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS) 45*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_4_CFG_OFFS 0x00002050 46*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_4_CFG(base) ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS) 47*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_5_CFG_OFFS 0x00002054 48*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_5_CFG(base) ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS) 49*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_6_CFG_OFFS 0x00002058 50*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_6_CFG(base) ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS) 51*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_7_CFG_OFFS 0x0000205C 52*4882a593Smuzhiyun #define FWSRAM_TOP_GPIO2_7_CFG(base) ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS) 53*4882a593Smuzhiyun #define FWSRAM_TOP_SCL_CFG_OFFS 0x00002060 54*4882a593Smuzhiyun #define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS) 55*4882a593Smuzhiyun #define FWSRAM_TOP_SDA_CFG_OFFS 0x00002064 56*4882a593Smuzhiyun #define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS) 57*4882a593Smuzhiyun #define FWSRAM_NO_MCM_FLASH_OFFS 0x00002068 58*4882a593Smuzhiyun #define FWSRAM_NO_MCM_FLASH(base) ((base) + FWSRAM_NO_MCM_FLASH_OFFS) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif 61