1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2006 Micronas GmbH 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _REG_EBI_PREMIUM_H_ 10*4882a593Smuzhiyun #define _REG_EBI_PREMIUM_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define EBI_BASE 0x00000000 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Relative offsets of the register adresses */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define EBI_CPU_IO_ACCS_OFFS 0x00000000 17*4882a593Smuzhiyun #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) 18*4882a593Smuzhiyun #define EBI_IO_ACCS_DATA_OFFS 0x00000004 19*4882a593Smuzhiyun #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) 20*4882a593Smuzhiyun #define EBI_CTRL_OFFS 0x00000008 21*4882a593Smuzhiyun #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) 22*4882a593Smuzhiyun #define EBI_IRQ_MASK_OFFS 0x00000010 23*4882a593Smuzhiyun #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) 24*4882a593Smuzhiyun #define EBI_TAG1_SYS_ID_OFFS 0x00000030 25*4882a593Smuzhiyun #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) 26*4882a593Smuzhiyun #define EBI_TAG2_SYS_ID_OFFS 0x00000040 27*4882a593Smuzhiyun #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) 28*4882a593Smuzhiyun #define EBI_TAG3_SYS_ID_OFFS 0x00000050 29*4882a593Smuzhiyun #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) 30*4882a593Smuzhiyun #define EBI_TAG4_SYS_ID_OFFS 0x00000060 31*4882a593Smuzhiyun #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) 32*4882a593Smuzhiyun #define EBI_GEN_DMA_CTRL_OFFS 0x00000070 33*4882a593Smuzhiyun #define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) 34*4882a593Smuzhiyun #define EBI_STATUS_OFFS 0x00000080 35*4882a593Smuzhiyun #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) 36*4882a593Smuzhiyun #define EBI_STATUS_DMA_CNT_OFFS 0x00000084 37*4882a593Smuzhiyun #define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) 38*4882a593Smuzhiyun #define EBI_SIG_LEVEL_OFFS 0x00000088 39*4882a593Smuzhiyun #define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) 40*4882a593Smuzhiyun #define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C 41*4882a593Smuzhiyun #define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) 42*4882a593Smuzhiyun #define EBI_EXT_ADDR_OFFS 0x000000A0 43*4882a593Smuzhiyun #define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) 44*4882a593Smuzhiyun #define EBI_IRQ_STATUS_OFFS 0x000000B0 45*4882a593Smuzhiyun #define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) 46*4882a593Smuzhiyun #define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 47*4882a593Smuzhiyun #define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) 48*4882a593Smuzhiyun #define EBI_DEV1_EXT_ACC_OFFS 0x00000104 49*4882a593Smuzhiyun #define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) 50*4882a593Smuzhiyun #define EBI_DEV1_CONFIG1_OFFS 0x00000108 51*4882a593Smuzhiyun #define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) 52*4882a593Smuzhiyun #define EBI_DEV1_CONFIG2_OFFS 0x0000010C 53*4882a593Smuzhiyun #define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) 54*4882a593Smuzhiyun #define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 55*4882a593Smuzhiyun #define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) 56*4882a593Smuzhiyun #define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 57*4882a593Smuzhiyun #define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) 58*4882a593Smuzhiyun #define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 59*4882a593Smuzhiyun #define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) 60*4882a593Smuzhiyun #define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C 61*4882a593Smuzhiyun #define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) 62*4882a593Smuzhiyun #define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 63*4882a593Smuzhiyun #define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) 64*4882a593Smuzhiyun #define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 65*4882a593Smuzhiyun #define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) 66*4882a593Smuzhiyun #define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C 67*4882a593Smuzhiyun #define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) 68*4882a593Smuzhiyun #define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 69*4882a593Smuzhiyun #define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) 70*4882a593Smuzhiyun #define EBI_DEV1_TIM_EXT_OFFS 0x00000134 71*4882a593Smuzhiyun #define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) 72*4882a593Smuzhiyun #define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 73*4882a593Smuzhiyun #define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) 74*4882a593Smuzhiyun #define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C 75*4882a593Smuzhiyun #define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) 76*4882a593Smuzhiyun #define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 77*4882a593Smuzhiyun #define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) 78*4882a593Smuzhiyun #define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 79*4882a593Smuzhiyun #define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) 80*4882a593Smuzhiyun #define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 81*4882a593Smuzhiyun #define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) 82*4882a593Smuzhiyun #define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 83*4882a593Smuzhiyun #define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) 84*4882a593Smuzhiyun #define EBI_DEV2_EXT_ACC_OFFS 0x00000204 85*4882a593Smuzhiyun #define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) 86*4882a593Smuzhiyun #define EBI_DEV2_CONFIG1_OFFS 0x00000208 87*4882a593Smuzhiyun #define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) 88*4882a593Smuzhiyun #define EBI_DEV2_CONFIG2_OFFS 0x0000020C 89*4882a593Smuzhiyun #define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) 90*4882a593Smuzhiyun #define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 91*4882a593Smuzhiyun #define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) 92*4882a593Smuzhiyun #define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 93*4882a593Smuzhiyun #define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) 94*4882a593Smuzhiyun #define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 95*4882a593Smuzhiyun #define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) 96*4882a593Smuzhiyun #define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C 97*4882a593Smuzhiyun #define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) 98*4882a593Smuzhiyun #define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 99*4882a593Smuzhiyun #define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) 100*4882a593Smuzhiyun #define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 101*4882a593Smuzhiyun #define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) 102*4882a593Smuzhiyun #define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C 103*4882a593Smuzhiyun #define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) 104*4882a593Smuzhiyun #define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 105*4882a593Smuzhiyun #define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) 106*4882a593Smuzhiyun #define EBI_DEV2_TIM_EXT_OFFS 0x00000234 107*4882a593Smuzhiyun #define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) 108*4882a593Smuzhiyun #define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 109*4882a593Smuzhiyun #define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) 110*4882a593Smuzhiyun #define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C 111*4882a593Smuzhiyun #define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) 112*4882a593Smuzhiyun #define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 113*4882a593Smuzhiyun #define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) 114*4882a593Smuzhiyun #define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 115*4882a593Smuzhiyun #define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) 116*4882a593Smuzhiyun #define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 117*4882a593Smuzhiyun #define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) 118*4882a593Smuzhiyun #define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 119*4882a593Smuzhiyun #define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) 120*4882a593Smuzhiyun #define EBI_DEV3_EXT_ACC_OFFS 0x00000304 121*4882a593Smuzhiyun #define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) 122*4882a593Smuzhiyun #define EBI_DEV3_CONFIG1_OFFS 0x00000308 123*4882a593Smuzhiyun #define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) 124*4882a593Smuzhiyun #define EBI_DEV3_CONFIG2_OFFS 0x0000030C 125*4882a593Smuzhiyun #define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) 126*4882a593Smuzhiyun #define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 127*4882a593Smuzhiyun #define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) 128*4882a593Smuzhiyun #define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 129*4882a593Smuzhiyun #define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) 130*4882a593Smuzhiyun #define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 131*4882a593Smuzhiyun #define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) 132*4882a593Smuzhiyun #define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C 133*4882a593Smuzhiyun #define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) 134*4882a593Smuzhiyun #define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 135*4882a593Smuzhiyun #define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) 136*4882a593Smuzhiyun #define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 137*4882a593Smuzhiyun #define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) 138*4882a593Smuzhiyun #define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C 139*4882a593Smuzhiyun #define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) 140*4882a593Smuzhiyun #define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 141*4882a593Smuzhiyun #define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) 142*4882a593Smuzhiyun #define EBI_DEV3_TIM_EXT_OFFS 0x00000334 143*4882a593Smuzhiyun #define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) 144*4882a593Smuzhiyun #define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 145*4882a593Smuzhiyun #define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) 146*4882a593Smuzhiyun #define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C 147*4882a593Smuzhiyun #define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) 148*4882a593Smuzhiyun #define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 149*4882a593Smuzhiyun #define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) 150*4882a593Smuzhiyun #define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 151*4882a593Smuzhiyun #define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) 152*4882a593Smuzhiyun #define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 153*4882a593Smuzhiyun #define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) 154*4882a593Smuzhiyun #define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 155*4882a593Smuzhiyun #define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) 156*4882a593Smuzhiyun #define EBI_DEV4_EXT_ACC_OFFS 0x00000404 157*4882a593Smuzhiyun #define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) 158*4882a593Smuzhiyun #define EBI_DEV4_CONFIG1_OFFS 0x00000408 159*4882a593Smuzhiyun #define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) 160*4882a593Smuzhiyun #define EBI_DEV4_CONFIG2_OFFS 0x0000040C 161*4882a593Smuzhiyun #define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) 162*4882a593Smuzhiyun #define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 163*4882a593Smuzhiyun #define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) 164*4882a593Smuzhiyun #define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 165*4882a593Smuzhiyun #define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) 166*4882a593Smuzhiyun #define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 167*4882a593Smuzhiyun #define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) 168*4882a593Smuzhiyun #define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C 169*4882a593Smuzhiyun #define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) 170*4882a593Smuzhiyun #define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 171*4882a593Smuzhiyun #define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) 172*4882a593Smuzhiyun #define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 173*4882a593Smuzhiyun #define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) 174*4882a593Smuzhiyun #define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C 175*4882a593Smuzhiyun #define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) 176*4882a593Smuzhiyun #define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 177*4882a593Smuzhiyun #define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) 178*4882a593Smuzhiyun #define EBI_DEV4_TIM_EXT_OFFS 0x00000434 179*4882a593Smuzhiyun #define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) 180*4882a593Smuzhiyun #define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 181*4882a593Smuzhiyun #define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) 182*4882a593Smuzhiyun #define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C 183*4882a593Smuzhiyun #define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) 184*4882a593Smuzhiyun #define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 185*4882a593Smuzhiyun #define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) 186*4882a593Smuzhiyun #define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 187*4882a593Smuzhiyun #define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) 188*4882a593Smuzhiyun #define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 189*4882a593Smuzhiyun #define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) 190*4882a593Smuzhiyun #define EBI_CNT_FL_PROGR_OFFS 0x00000904 191*4882a593Smuzhiyun #define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) 192*4882a593Smuzhiyun #define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C 193*4882a593Smuzhiyun #define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) 194*4882a593Smuzhiyun #define EBI_CNT_WAIT_RDY_OFFS 0x00000914 195*4882a593Smuzhiyun #define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) 196*4882a593Smuzhiyun #define EBI_CNT_ACK_OFFS 0x00000918 197*4882a593Smuzhiyun #define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) 198*4882a593Smuzhiyun #define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 199*4882a593Smuzhiyun #define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) 200*4882a593Smuzhiyun #define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 201*4882a593Smuzhiyun #define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) 202*4882a593Smuzhiyun #define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 203*4882a593Smuzhiyun #define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) 204*4882a593Smuzhiyun #define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 205*4882a593Smuzhiyun #define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) 206*4882a593Smuzhiyun #define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 207*4882a593Smuzhiyun #define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) 208*4882a593Smuzhiyun #define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 209*4882a593Smuzhiyun #define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) 210*4882a593Smuzhiyun #define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 211*4882a593Smuzhiyun #define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) 212*4882a593Smuzhiyun #define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 213*4882a593Smuzhiyun #define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) 214*4882a593Smuzhiyun #define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 215*4882a593Smuzhiyun #define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) 216*4882a593Smuzhiyun #define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 217*4882a593Smuzhiyun #define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) 218*4882a593Smuzhiyun #define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 219*4882a593Smuzhiyun #define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) 220*4882a593Smuzhiyun #define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 221*4882a593Smuzhiyun #define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) 222*4882a593Smuzhiyun #define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 223*4882a593Smuzhiyun #define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) 224*4882a593Smuzhiyun #define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 225*4882a593Smuzhiyun #define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) 226*4882a593Smuzhiyun #define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 227*4882a593Smuzhiyun #define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun #endif 230