1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2006 Micronas GmbH 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <asm/io.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "bcu.h" 12*4882a593Smuzhiyun #include "dcgu.h" 13*4882a593Smuzhiyun #include "ebi.h" 14*4882a593Smuzhiyun #include "scc.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifdef CONFIG_VCT_PREMIUM 17*4882a593Smuzhiyun /* Global start address of all memory mapped registers */ 18*4882a593Smuzhiyun #define REG_GLOBAL_START_ADDR 0xbf800000 19*4882a593Smuzhiyun #define TOP_BASE 0x000c8000 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #include "vcth/reg_ebi.h" 22*4882a593Smuzhiyun #include "vcth/reg_dcgu.h" 23*4882a593Smuzhiyun #include "vcth/reg_wdt.h" 24*4882a593Smuzhiyun #include "vcth/reg_gpio.h" 25*4882a593Smuzhiyun #include "vcth/reg_fwsram.h" 26*4882a593Smuzhiyun #include "vcth/reg_scc.h" 27*4882a593Smuzhiyun #include "vcth/reg_usbh.h" 28*4882a593Smuzhiyun #endif 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #ifdef CONFIG_VCT_PLATINUM 31*4882a593Smuzhiyun /* Global start address of all memory mapped registers */ 32*4882a593Smuzhiyun #define REG_GLOBAL_START_ADDR 0xbf800000 33*4882a593Smuzhiyun #define TOP_BASE 0x000c8000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #include "vcth2/reg_ebi.h" 36*4882a593Smuzhiyun #include "vcth/reg_dcgu.h" 37*4882a593Smuzhiyun #include "vcth/reg_wdt.h" 38*4882a593Smuzhiyun #include "vcth/reg_gpio.h" 39*4882a593Smuzhiyun #include "vcth/reg_fwsram.h" 40*4882a593Smuzhiyun #include "vcth/reg_scc.h" 41*4882a593Smuzhiyun #include "vcth/reg_usbh.h" 42*4882a593Smuzhiyun #endif 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #ifdef CONFIG_VCT_PLATINUMAVC 45*4882a593Smuzhiyun /* Global start address of all memory mapped registers */ 46*4882a593Smuzhiyun #define REG_GLOBAL_START_ADDR 0xbdc00000 47*4882a593Smuzhiyun #define TOP_BASE 0x00050000 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #include "vctv/reg_ebi.h" 50*4882a593Smuzhiyun #include "vctv/reg_dcgu.h" 51*4882a593Smuzhiyun #include "vctv/reg_wdt.h" 52*4882a593Smuzhiyun #include "vctv/reg_gpio.h" 53*4882a593Smuzhiyun #endif 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #ifndef _VCT_H 56*4882a593Smuzhiyun #define _VCT_H 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * Defines 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun #define PRID_COMP_LEGACY 0x000000 62*4882a593Smuzhiyun #define PRID_COMP_MIPS 0x010000 63*4882a593Smuzhiyun #define PRID_IMP_LX4280 0xc200 64*4882a593Smuzhiyun #define PRID_IMP_VGC 0x9000 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* 67*4882a593Smuzhiyun * Prototypes 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun int ebi_initialize(void); 70*4882a593Smuzhiyun int ebi_init_nor_flash(void); 71*4882a593Smuzhiyun int ebi_init_onenand(void); 72*4882a593Smuzhiyun int ebi_init_smc911x(void); 73*4882a593Smuzhiyun u32 smc911x_reg_read(u32 addr); 74*4882a593Smuzhiyun void smc911x_reg_write(u32 addr, u32 data); 75*4882a593Smuzhiyun int top_set_pin(int pin, int func); 76*4882a593Smuzhiyun void vct_pin_mux_initialize(void); 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * static inlines 80*4882a593Smuzhiyun */ reg_write(u32 addr,u32 data)81*4882a593Smuzhiyunstatic inline void reg_write(u32 addr, u32 data) 82*4882a593Smuzhiyun { 83*4882a593Smuzhiyun void *reg = (void *)(addr + REG_GLOBAL_START_ADDR); 84*4882a593Smuzhiyun __raw_writel(data, reg); 85*4882a593Smuzhiyun } 86*4882a593Smuzhiyun reg_read(u32 addr)87*4882a593Smuzhiyunstatic inline u32 reg_read(u32 addr) 88*4882a593Smuzhiyun { 89*4882a593Smuzhiyun const void *reg = (const void *)(addr + REG_GLOBAL_START_ADDR); 90*4882a593Smuzhiyun return __raw_readl(reg); 91*4882a593Smuzhiyun } 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif /* _VCT_H */ 94