1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Original Author Guenter Gebhardt
5*4882a593Smuzhiyun * Copyright (C) 2006 Micronas GmbH
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "vct.h"
13*4882a593Smuzhiyun
vct_ehci_hcd_init(u32 * hccr,u32 * hcor)14*4882a593Smuzhiyun int vct_ehci_hcd_init(u32 *hccr, u32 *hcor)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun int retval;
17*4882a593Smuzhiyun u32 val;
18*4882a593Smuzhiyun u32 addr;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
21*4882a593Smuzhiyun dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
22*4882a593Smuzhiyun dcgu_set_clk_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
23*4882a593Smuzhiyun dcgu_set_clk_switch(DCGU_HW_MODULE_USB_PLL, DCGU_SWITCH_ON);
24*4882a593Smuzhiyun dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_OFF);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Wait until (DCGU_USBPHY_STAT == 7) */
27*4882a593Smuzhiyun addr = DCGU_USBPHY_STAT(DCGU_BASE);
28*4882a593Smuzhiyun val = reg_read(addr);
29*4882a593Smuzhiyun while (val != 7)
30*4882a593Smuzhiyun val = reg_read(addr);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun dcgu_set_clk_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
33*4882a593Smuzhiyun dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_OFF);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun retval = scc_reset(SCC_USB_RW, 0);
36*4882a593Smuzhiyun if (retval) {
37*4882a593Smuzhiyun printf("scc_reset(SCC_USB_RW, 0) returned: 0x%x\n", retval);
38*4882a593Smuzhiyun return retval;
39*4882a593Smuzhiyun } else {
40*4882a593Smuzhiyun retval = scc_reset(SCC_CPU1_SPDMA_RW, 0);
41*4882a593Smuzhiyun if (retval) {
42*4882a593Smuzhiyun printf("scc_reset(SCC_CPU1_SPDMA_RW, 0) returned: 0x%x\n",
43*4882a593Smuzhiyun retval);
44*4882a593Smuzhiyun return retval;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (!retval) {
49*4882a593Smuzhiyun /*
50*4882a593Smuzhiyun * For the AGU bypass, where the SCC client provides full
51*4882a593Smuzhiyun * physical address
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun scc_set_usb_address_generation_mode(1);
54*4882a593Smuzhiyun scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
55*4882a593Smuzhiyun USE_NO_FH, DMA_READ, 0);
56*4882a593Smuzhiyun scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
57*4882a593Smuzhiyun USE_NO_FH, DMA_WRITE, 0);
58*4882a593Smuzhiyun scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
59*4882a593Smuzhiyun USE_NO_FH, DMA_WRITE, 0);
60*4882a593Smuzhiyun scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
61*4882a593Smuzhiyun USE_NO_FH, DMA_READ, 0);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Enable memory interface */
64*4882a593Smuzhiyun scc_enable(SCC_USB_RW, 1);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Start (start_cmd=0) DMAs */
67*4882a593Smuzhiyun scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_READ);
68*4882a593Smuzhiyun scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_WRITE);
69*4882a593Smuzhiyun } else {
70*4882a593Smuzhiyun printf("Cannot configure USB memory channel.\n");
71*4882a593Smuzhiyun printf("USB can not access RAM. SCC configuration failed.\n");
72*4882a593Smuzhiyun return retval;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Wait a short while */
76*4882a593Smuzhiyun udelay(300000);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* Set EHCI structures and DATA in RAM */
81*4882a593Smuzhiyun reg_write(USBH_USBHMISC(USBH_BASE), 0x00840003);
82*4882a593Smuzhiyun /* Set USBMODE to bigendian and set host mode */
83*4882a593Smuzhiyun reg_write(USBH_USBMODE(USBH_BASE), 0x00000007);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /*
86*4882a593Smuzhiyun * USBH_BURSTSIZE MUST EQUAL 0x00001c1c in order for
87*4882a593Smuzhiyun * 512 byte USB transfers on the bulk pipe to work properly.
88*4882a593Smuzhiyun * Set USBH_BURSTSIZE to 0x00001c1c
89*4882a593Smuzhiyun */
90*4882a593Smuzhiyun reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* Insert access register addresses */
93*4882a593Smuzhiyun *hccr = REG_GLOBAL_START_ADDR + USBH_CAPLENGTH(USBH_BASE);
94*4882a593Smuzhiyun *hcor = REG_GLOBAL_START_ADDR + USBH_USBCMD(USBH_BASE);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98