1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __EBI__ 8*4882a593Smuzhiyun #define __EBI__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <asm/io.h> 12*4882a593Smuzhiyun #include "vct.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define EXT_DEVICE_CHANNEL_3 (0x30000000) 15*4882a593Smuzhiyun #define EXT_DEVICE_CHANNEL_2 (0x20000000) 16*4882a593Smuzhiyun #define EXT_DEVICE_CHANNEL_1 (0x10000000) 17*4882a593Smuzhiyun #define EXT_CPU_ACCESS_ACTIVE (0x00000001) 18*4882a593Smuzhiyun #define EXT_DMA_ACCESS_ACTIVE (1 << 14) 19*4882a593Smuzhiyun #define EXT_CPU_IORDY_SL (0x00000001) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define EBI_CPU_WRITE (1 << 31) 22*4882a593Smuzhiyun #define EBI_CPU_ID_SHIFT (28) 23*4882a593Smuzhiyun #define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */ 26*4882a593Smuzhiyun #define ADDR_LATCH_ENABLE 0 27*4882a593Smuzhiyun #define ADDR_ACTIVATION 4 28*4882a593Smuzhiyun #define CHIP_SELECT_START 8 29*4882a593Smuzhiyun #define OUTPUT_ENABLE_START 12 30*4882a593Smuzhiyun #define WAIT_TIME 28 31*4882a593Smuzhiyun #define READ_DURATION 20 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */ 34*4882a593Smuzhiyun #define OUTPUT_ENABLE_END 0 35*4882a593Smuzhiyun #define CHIP_SELECT_END 4 36*4882a593Smuzhiyun #define ADDR_DEACTIVATION 8 37*4882a593Smuzhiyun #define RECOVER_TIME 12 38*4882a593Smuzhiyun #define ACK_TIME 20 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* various bits in configuration register EBI_DEV[01]_CONFIG1 */ 41*4882a593Smuzhiyun #define EBI_EXTERNAL_DATA_8 (1 << 8) 42*4882a593Smuzhiyun #define EBI_EXT_ADDR_SHIFT (1 << 22) 43*4882a593Smuzhiyun #define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT 44*4882a593Smuzhiyun #define EBI_CHIP_SELECT_1 0x2 45*4882a593Smuzhiyun #define EBI_CHIP_SELECT_2 0x4 46*4882a593Smuzhiyun #define EBI_BUSY_EN_RD (1 << 12) 47*4882a593Smuzhiyun #define DIR_ACCESS_WRITE (1 << 20) 48*4882a593Smuzhiyun #define DIR_ACCESS_MASK (1 << 20) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* various bits in configuration register EBI_DEV[01]_CONFIG2 */ 51*4882a593Smuzhiyun #define ADDRESS_INCREMENT_ON 0x0 52*4882a593Smuzhiyun #define ADDRESS_INCREMENT_OFF 0x100 53*4882a593Smuzhiyun #define QUEUE_LENGTH_1 0x40 54*4882a593Smuzhiyun #define QUEUE_LENGTH_2 0x80 55*4882a593Smuzhiyun #define QUEUE_LENGTH_3 0xC0 56*4882a593Smuzhiyun #define QUEUE_LENGTH_4 0 57*4882a593Smuzhiyun #define CPU_TRANSFER_SIZE_32 0 58*4882a593Smuzhiyun #define CPU_TRANSFER_SIZE_16 0x10 59*4882a593Smuzhiyun #define CPU_TRANSFER_SIZE_8 0x20 60*4882a593Smuzhiyun #define READ_ENDIANNESS_ABCD 0 61*4882a593Smuzhiyun #define READ_ENDIANNESS_DCBA 0x4 62*4882a593Smuzhiyun #define READ_ENDIANNESS_BADC 0x8 63*4882a593Smuzhiyun #define READ_ENDIANNESS_CDAB 0xC 64*4882a593Smuzhiyun #define WRITE_ENDIANNESS_ABCD 0 65*4882a593Smuzhiyun #define WRITE_ENDIANNESS_DCBA 0x1 66*4882a593Smuzhiyun #define WRITE_ENDIANNESS_BADC 0x2 67*4882a593Smuzhiyun #define WRITE_ENDIANNESS_CDAB 0x3 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* various bits in configuration register EBI_CTRL_SIG_ACTLV */ 70*4882a593Smuzhiyun #define IORDY_ACTIVELEVEL_HIGH (1 << 14) 71*4882a593Smuzhiyun #define ALE_ACTIVELEVEL_HIGH (1 << 8) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* bits in register EBI_SIG_LEVEL */ 74*4882a593Smuzhiyun #define IORDY_LEVEL_MASK 1 75*4882a593Smuzhiyun ebi_wait(void)76*4882a593Smuzhiyunstatic inline void ebi_wait(void) 77*4882a593Smuzhiyun { 78*4882a593Smuzhiyun while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE) 79*4882a593Smuzhiyun ; /* wait */ 80*4882a593Smuzhiyun } 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #endif 83