1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008 3*4882a593Smuzhiyun * Texas Instruments 4*4882a593Smuzhiyun * Nishanth Menon <nm@ti.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Derived from: board/omap3/beagle/beagle.h 7*4882a593Smuzhiyun * Dirk Behme <dirk.behme@gmail.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef _BOARD_ZOOM1_H_ 12*4882a593Smuzhiyun #define _BOARD_ZOOM1_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun const omap3_sysinfo sysinfo = { 15*4882a593Smuzhiyun DDR_STACKED, 16*4882a593Smuzhiyun "OMAP3 Zoom MDK Rev 1", 17*4882a593Smuzhiyun "NAND", 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define ZOOM1_ENET_GPMC_CONF1 0x00611000 21*4882a593Smuzhiyun #define ZOOM1_ENET_GPMC_CONF2 0x001F1F01 22*4882a593Smuzhiyun #define ZOOM1_ENET_GPMC_CONF3 0x00080803 23*4882a593Smuzhiyun #define ZOOM1_ENET_GPMC_CONF4 0x1D091D09 24*4882a593Smuzhiyun #define ZOOM1_ENET_GPMC_CONF5 0x041D1F1F 25*4882a593Smuzhiyun #define ZOOM1_ENET_GPMC_CONF6 0x1D0904C4 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * IEN - Input Enable 29*4882a593Smuzhiyun * IDIS - Input Disable 30*4882a593Smuzhiyun * PTD - Pull type Down 31*4882a593Smuzhiyun * PTU - Pull type Up 32*4882a593Smuzhiyun * DIS - Pull type selection is inactive 33*4882a593Smuzhiyun * EN - Pull type selection is active 34*4882a593Smuzhiyun * M0 - Mode 0 35*4882a593Smuzhiyun * The commented string gives the final mux configuration for that pin 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #define MUX_ZOOM1_MDK() \ 38*4882a593Smuzhiyun /*SDRC*/\ 39*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ 40*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ 41*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ 42*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ 43*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ 44*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ 45*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ 46*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ 47*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ 48*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ 49*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ 50*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ 51*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ 52*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ 53*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ 54*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ 55*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ 56*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ 57*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ 58*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ 59*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ 60*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ 61*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ 62*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ 63*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ 64*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ 65*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ 66*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ 67*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ 68*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ 69*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ 70*4882a593Smuzhiyun MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ 71*4882a593Smuzhiyun MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ 72*4882a593Smuzhiyun MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ 73*4882a593Smuzhiyun MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ 74*4882a593Smuzhiyun MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ 75*4882a593Smuzhiyun MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ 76*4882a593Smuzhiyun /*GPMC*/\ 77*4882a593Smuzhiyun MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ 78*4882a593Smuzhiyun MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ 79*4882a593Smuzhiyun MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ 80*4882a593Smuzhiyun MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ 81*4882a593Smuzhiyun MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ 82*4882a593Smuzhiyun MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ 83*4882a593Smuzhiyun MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ 84*4882a593Smuzhiyun MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ 85*4882a593Smuzhiyun MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ 86*4882a593Smuzhiyun MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ 87*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ 88*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ 89*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ 90*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ 91*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ 92*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ 93*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ 94*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ 95*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ 96*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ 97*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ 98*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ 99*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ 100*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ 101*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ 102*4882a593Smuzhiyun MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ 103*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ 104*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ 105*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\ 106*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | DIS | M4)) /*GPMC_nCS3 -> GPIO54*/\ 107*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M4)) /*GPMC_nCS4 -> GPIO 55*/\ 108*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)) /*GPMC_nCS5 -> GPIO 56*/\ 109*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\ 110*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7 -> GPMC_IO_DIR*/\ 111*4882a593Smuzhiyun MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ 112*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ 113*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ 114*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ 115*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /*GPMC_nWP*/\ 116*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ 117*4882a593Smuzhiyun MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\ 118*4882a593Smuzhiyun MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /*GPMC_WAIT0*/\ 119*4882a593Smuzhiyun MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ 120*4882a593Smuzhiyun MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\ 121*4882a593Smuzhiyun MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif /* _BOARD_ZOOM_H_ */ 124