1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2013 Keymile AG 3*4882a593Smuzhiyun * Valentin Longchamp <valentin.longchamp@keymile.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2008-2011 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 2000 8*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <common.h> 14*4882a593Smuzhiyun #include <asm/mmu.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 17*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 18*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 19*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS, 20*4882a593Smuzhiyun MAS3_SW|MAS3_SR, 0, 21*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 22*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 23*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 24*4882a593Smuzhiyun MAS3_SW|MAS3_SR, 0, 25*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 26*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 27*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 28*4882a593Smuzhiyun MAS3_SW|MAS3_SR, 0, 29*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 30*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 31*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 32*4882a593Smuzhiyun MAS3_SW|MAS3_SR, 0, 33*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 34*4882a593Smuzhiyun /* TLB 1 */ 35*4882a593Smuzhiyun /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 36*4882a593Smuzhiyun * SRAM is at 0xfff00000, it covered the 0xfffff000. 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 39*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 40*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_1M, 1), 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* *I*G* - CCSRBAR */ 43*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 44*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 45*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_16M, 1), 46*4882a593Smuzhiyun /* QRIO */ 47*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, 48*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 49*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_64K, 1), 50*4882a593Smuzhiyun /* *I*G* - PCI1 */ 51*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 52*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 53*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_512M, 1), 54*4882a593Smuzhiyun /* *I*G* - PCI3 */ 55*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, 56*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_512M, 1), 58*4882a593Smuzhiyun /* *I*G* - PCI1&3 I/O */ 59*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 60*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 61*4882a593Smuzhiyun 0, 6, BOOKE_PAGESZ_128K, 1), 62*4882a593Smuzhiyun #ifdef CONFIG_SYS_LBAPP1_BASE_PHYS 63*4882a593Smuzhiyun /* LBAPP1 */ 64*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS, 65*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 66*4882a593Smuzhiyun 0, 7, BOOKE_PAGESZ_256M, 1), 67*4882a593Smuzhiyun #endif 68*4882a593Smuzhiyun #ifdef CONFIG_SYS_LBAPP2_BASE_PHYS 69*4882a593Smuzhiyun /* LBAPP2 */ 70*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS, 71*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 72*4882a593Smuzhiyun 0, 8, BOOKE_PAGESZ_256M, 1), 73*4882a593Smuzhiyun #endif 74*4882a593Smuzhiyun /* Bman/Qman */ 75*4882a593Smuzhiyun #ifdef CONFIG_SYS_BMAN_MEM_PHYS 76*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 77*4882a593Smuzhiyun MAS3_SW|MAS3_SR, 0, 78*4882a593Smuzhiyun 0, 9, BOOKE_PAGESZ_1M, 1), 79*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 80*4882a593Smuzhiyun CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 81*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 82*4882a593Smuzhiyun 0, 10, BOOKE_PAGESZ_1M, 1), 83*4882a593Smuzhiyun #endif 84*4882a593Smuzhiyun #ifdef CONFIG_SYS_QMAN_MEM_PHYS 85*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 86*4882a593Smuzhiyun MAS3_SW|MAS3_SR, 0, 87*4882a593Smuzhiyun 0, 11, BOOKE_PAGESZ_1M, 1), 88*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 89*4882a593Smuzhiyun CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 90*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 91*4882a593Smuzhiyun 0, 12, BOOKE_PAGESZ_1M, 1), 92*4882a593Smuzhiyun #endif 93*4882a593Smuzhiyun #ifdef CONFIG_SYS_DCSRBAR_PHYS 94*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 95*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 96*4882a593Smuzhiyun 0, 13, BOOKE_PAGESZ_4M, 1), 97*4882a593Smuzhiyun #endif 98*4882a593Smuzhiyun #ifdef CONFIG_SYS_NAND_BASE 99*4882a593Smuzhiyun /* 100*4882a593Smuzhiyun * *I*G - NAND 101*4882a593Smuzhiyun * entry 14 and 15 has been used hard coded, they will be disabled 102*4882a593Smuzhiyun * in cpu_init_f, so we use entry 16 for nand. 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 105*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 106*4882a593Smuzhiyun 0, 16, BOOKE_PAGESZ_32K, 1), 107*4882a593Smuzhiyun #endif 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 111