1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2013 Keymile AG
3*4882a593Smuzhiyun * Valentin Longchamp <valentin.longchamp@keymile.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2007-2011 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <command.h>
12*4882a593Smuzhiyun #include <pci.h>
13*4882a593Smuzhiyun #include <asm/fsl_pci.h>
14*4882a593Smuzhiyun #include <linux/libfdt.h>
15*4882a593Smuzhiyun #include <fdt_support.h>
16*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
17*4882a593Smuzhiyun #include <linux/errno.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "kmp204x.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define PROM_SEL_L 11
22*4882a593Smuzhiyun /* control the PROM_SEL_L signal*/
toggle_fpga_eeprom_bus(bool cpu_own)23*4882a593Smuzhiyun static void toggle_fpga_eeprom_bus(bool cpu_own)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own);
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define CONF_SEL_L 10
29*4882a593Smuzhiyun #define FPGA_PROG_L 19
30*4882a593Smuzhiyun #define FPGA_DONE 18
31*4882a593Smuzhiyun #define FPGA_INIT_L 17
32*4882a593Smuzhiyun
trigger_fpga_config(void)33*4882a593Smuzhiyun int trigger_fpga_config(void)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun int ret = 0, init_l;
36*4882a593Smuzhiyun /* approx 10ms */
37*4882a593Smuzhiyun u32 timeout = 10000;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* make sure the FPGA_can access the EEPROM */
40*4882a593Smuzhiyun toggle_fpga_eeprom_bus(false);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* assert CONF_SEL_L to be able to drive FPGA_PROG_L */
43*4882a593Smuzhiyun qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* trigger the config start */
46*4882a593Smuzhiyun qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* small delay for INIT_L line */
49*4882a593Smuzhiyun udelay(10);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* wait for FPGA_INIT to be asserted */
52*4882a593Smuzhiyun do {
53*4882a593Smuzhiyun init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L);
54*4882a593Smuzhiyun if (timeout-- == 0) {
55*4882a593Smuzhiyun printf("FPGA_INIT timeout\n");
56*4882a593Smuzhiyun ret = -EFAULT;
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun udelay(10);
60*4882a593Smuzhiyun } while (init_l);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* deassert FPGA_PROG, config should start */
63*4882a593Smuzhiyun qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return ret;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */
wait_for_fpga_config(void)69*4882a593Smuzhiyun static int wait_for_fpga_config(void)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun int ret = 0, done;
72*4882a593Smuzhiyun /* approx 5 s */
73*4882a593Smuzhiyun u32 timeout = 500000;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun printf("PCIe FPGA config:");
76*4882a593Smuzhiyun do {
77*4882a593Smuzhiyun done = qrio_get_gpio(GPIO_A, FPGA_DONE);
78*4882a593Smuzhiyun if (timeout-- == 0) {
79*4882a593Smuzhiyun printf(" FPGA_DONE timeout\n");
80*4882a593Smuzhiyun ret = -EFAULT;
81*4882a593Smuzhiyun goto err_out;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun udelay(10);
84*4882a593Smuzhiyun } while (!done);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun printf(" done\n");
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun err_out:
89*4882a593Smuzhiyun /* deactive CONF_SEL and give the CPU conf EEPROM access */
90*4882a593Smuzhiyun qrio_set_gpio(GPIO_A, CONF_SEL_L, 1);
91*4882a593Smuzhiyun toggle_fpga_eeprom_bus(true);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun return ret;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #define PCIE_SW_RST 14
97*4882a593Smuzhiyun #define PEXHC_RST 13
98*4882a593Smuzhiyun #define HOOPER_RST 12
99*4882a593Smuzhiyun
pci_init_board(void)100*4882a593Smuzhiyun void pci_init_board(void)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
103*4882a593Smuzhiyun qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
104*4882a593Smuzhiyun qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* wait for the PCIe FPGA to be configured
107*4882a593Smuzhiyun * it has been triggered earlier in board_early_init_r */
108*4882a593Smuzhiyun if (wait_for_fpga_config())
109*4882a593Smuzhiyun printf("error finishing PCIe FPGA config\n");
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun qrio_prst(PCIE_SW_RST, false, false);
112*4882a593Smuzhiyun qrio_prst(PEXHC_RST, false, false);
113*4882a593Smuzhiyun qrio_prst(HOOPER_RST, false, false);
114*4882a593Smuzhiyun /* Hooper is not direcly PCIe capable */
115*4882a593Smuzhiyun mdelay(50);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun fsl_pcie_init_board(0);
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
pci_of_setup(void * blob,bd_t * bd)120*4882a593Smuzhiyun void pci_of_setup(void *blob, bd_t *bd)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun FT_FSL_PCI_SETUP;
123*4882a593Smuzhiyun }
124