1*4882a593Smuzhiyun# 2*4882a593Smuzhiyun# Copyright 2012 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun# 4*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun# 6*4882a593Smuzhiyun# Refer docs/README.pblimage for more details about how-to configure 7*4882a593Smuzhiyun# and create PBL boot image 8*4882a593Smuzhiyun# 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#PBI commands 11*4882a593Smuzhiyun#Configure ALTCBAR for DCSR -> DCSR@89000000 12*4882a593Smuzhiyun091380c0 000009C4 13*4882a593Smuzhiyun09000010 00000000 14*4882a593Smuzhiyun091380c0 000009C4 15*4882a593Smuzhiyun09000014 00000000 16*4882a593Smuzhiyun091380c0 000009C4 17*4882a593Smuzhiyun09000018 81d00000 18*4882a593Smuzhiyun#Workaround for A-004849 19*4882a593Smuzhiyun091380c0 000009C4 20*4882a593Smuzhiyun890B0050 00000002 21*4882a593Smuzhiyun091380c0 000009C4 22*4882a593Smuzhiyun890B0054 00000002 23*4882a593Smuzhiyun091380c0 000009C4 24*4882a593Smuzhiyun890B0058 00000002 25*4882a593Smuzhiyun091380c0 000009C4 26*4882a593Smuzhiyun890B005C 00000002 27*4882a593Smuzhiyun091380c0 000009C4 28*4882a593Smuzhiyun890B0090 00000002 29*4882a593Smuzhiyun091380c0 000009C4 30*4882a593Smuzhiyun890B0094 00000002 31*4882a593Smuzhiyun091380c0 000009C4 32*4882a593Smuzhiyun890B0098 00000002 33*4882a593Smuzhiyun091380c0 000009C4 34*4882a593Smuzhiyun890B009C 00000002 35*4882a593Smuzhiyun091380c0 000009C4 36*4882a593Smuzhiyun890B0108 00000012 37*4882a593Smuzhiyun091380c0 000009C4 38*4882a593Smuzhiyun#Workaround for A-006559 needed for rev 2.0 of P2041 silicon 39*4882a593Smuzhiyun89021008 0000f000 40*4882a593Smuzhiyun091380c0 000009C4 41*4882a593Smuzhiyun89021028 0000f000 42*4882a593Smuzhiyun091380c0 000009C4 43*4882a593Smuzhiyun89021048 0000f000 44*4882a593Smuzhiyun091380c0 000009C4 45*4882a593Smuzhiyun89021068 0000f000 46*4882a593Smuzhiyun091380c0 000009C4 47*4882a593Smuzhiyun#Flush PBL data 48*4882a593Smuzhiyun09138000 00000000 49*4882a593Smuzhiyun#Disable ALTCBAR 50*4882a593Smuzhiyun09000018 00000000 51*4882a593Smuzhiyun091380c0 000009C4 52*4882a593Smuzhiyun#Initialize CPC1 as 1MB SRAM 53*4882a593Smuzhiyun09010000 00200400 54*4882a593Smuzhiyun09138000 00000000 55*4882a593Smuzhiyun091380c0 00000100 56*4882a593Smuzhiyun09010100 00000000 57*4882a593Smuzhiyun09010104 fff0000b 58*4882a593Smuzhiyun09010f00 08000000 59*4882a593Smuzhiyun09010000 80000000 60*4882a593Smuzhiyun#Configure LAW for CPC1 61*4882a593Smuzhiyun09000d00 00000000 62*4882a593Smuzhiyun09000d04 fff00000 63*4882a593Smuzhiyun09000d08 81000013 64*4882a593Smuzhiyun09000010 00000000 65*4882a593Smuzhiyun09000014 ff000000 66*4882a593Smuzhiyun09000018 81000000 67*4882a593Smuzhiyun#Initialize eSPI controller, default configuration is slow for eSPI to 68*4882a593Smuzhiyun#load data, this configuration comes from u-boot eSPI driver. 69*4882a593Smuzhiyun09110000 80000403 70*4882a593Smuzhiyun09110020 27170008 71*4882a593Smuzhiyun09110024 00100008 72*4882a593Smuzhiyun09110028 00100008 73*4882a593Smuzhiyun0911002c 00100008 74*4882a593Smuzhiyun#Flush PBL data 75*4882a593Smuzhiyun09138000 00000000 76*4882a593Smuzhiyun091380c0 00000000 77