1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2013 Keymile AG 3*4882a593Smuzhiyun * Valentin Longchamp <valentin.longchamp@keymile.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2008-2011 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 2000 8*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <common.h> 14*4882a593Smuzhiyun #include <asm/fsl_law.h> 15*4882a593Smuzhiyun #include <asm/mmu.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct law_entry law_table[] = { 18*4882a593Smuzhiyun #ifdef CONFIG_SYS_BMAN_MEM_PHYS 19*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), 20*4882a593Smuzhiyun #endif 21*4882a593Smuzhiyun #ifdef CONFIG_SYS_QMAN_MEM_PHYS 22*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun #ifdef CONFIG_SYS_DCSRBAR_PHYS 25*4882a593Smuzhiyun /* Limit DCSR to 32M to access NPC Trace Buffer */ 26*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), 27*4882a593Smuzhiyun #endif 28*4882a593Smuzhiyun #ifdef CONFIG_SYS_NAND_BASE_PHYS 29*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), 30*4882a593Smuzhiyun #endif 31*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), 32*4882a593Smuzhiyun #ifdef CONFIG_SYS_LBAPP1_BASE_PHYS 33*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_LBAPP1_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), 34*4882a593Smuzhiyun #endif 35*4882a593Smuzhiyun #ifdef CONFIG_SYS_LBAPP2_BASE_PHYS 36*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_LBAPP2_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), 37*4882a593Smuzhiyun #endif 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun int num_law_entries = ARRAY_SIZE(law_table); 41