1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2013 Keymile AG
3*4882a593Smuzhiyun * Valentin Longchamp <valentin.longchamp@keymile.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <netdev.h>
10*4882a593Smuzhiyun #include <fm_eth.h>
11*4882a593Smuzhiyun #include <fsl_mdio.h>
12*4882a593Smuzhiyun #include <phy.h>
13*4882a593Smuzhiyun
board_eth_init(bd_t * bis)14*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun int ret = 0;
17*4882a593Smuzhiyun #ifdef CONFIG_FMAN_ENET
18*4882a593Smuzhiyun struct fsl_pq_mdio_info dtsec_mdio_info;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun printf("Initializing Fman\n");
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun dtsec_mdio_info.regs =
23*4882a593Smuzhiyun (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
24*4882a593Smuzhiyun dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Register the real 1G MDIO bus */
27*4882a593Smuzhiyun fsl_pq_mdio_init(bis, &dtsec_mdio_info);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* DTESC1/2 don't have a PHY, they are temporarily disabled
30*4882a593Smuzhiyun * so that u-boot doesn't try to unsuccessfuly enable them */
31*4882a593Smuzhiyun fm_disable_port(FM1_DTSEC1);
32*4882a593Smuzhiyun fm_disable_port(FM1_DTSEC2);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /*
35*4882a593Smuzhiyun * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf
36*4882a593Smuzhiyun * This is the debug interface, the only one used in u-boot
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
39*4882a593Smuzhiyun fm_info_set_mdio(FM1_DTSEC5,
40*4882a593Smuzhiyun miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun ret = cpu_eth_init(bis);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* reenable DTSEC1/2 for later (kernel) */
45*4882a593Smuzhiyun fm_enable_port(FM1_DTSEC1);
46*4882a593Smuzhiyun fm_enable_port(FM1_DTSEC2);
47*4882a593Smuzhiyun #endif
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return ret;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL)
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define mv88E1118_PAGE_REG 22
55*4882a593Smuzhiyun
board_phy_config(struct phy_device * phydev)56*4882a593Smuzhiyun int board_phy_config(struct phy_device *phydev)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) {
59*4882a593Smuzhiyun /* driver config is good */
60*4882a593Smuzhiyun if (phydev->drv->config)
61*4882a593Smuzhiyun phydev->drv->config(phydev);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* but we still need to fix the LEDs */
64*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003);
65*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840);
66*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun #endif
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