1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008 3*4882a593Smuzhiyun * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __KEYMILE_COMMON_H 9*4882a593Smuzhiyun #define __KEYMILE_COMMON_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define WRG_RESET 0x80 12*4882a593Smuzhiyun #define H_OPORTS_14 0x40 13*4882a593Smuzhiyun #define WRG_LED 0x02 14*4882a593Smuzhiyun #define WRL_BOOT 0x01 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define OPRTL_XBUFENA 0x20 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define H_OPORTS_SCC4_ENA 0x10 19*4882a593Smuzhiyun #define H_OPORTS_SCC4_FD_ENA 0x04 20*4882a593Smuzhiyun #define H_OPORTS_FCC1_PW_DWN 0x01 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define PIGGY_PRESENT 0x80 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct km_bec_fpga { 25*4882a593Smuzhiyun unsigned char id; 26*4882a593Smuzhiyun unsigned char rev; 27*4882a593Smuzhiyun unsigned char oprth; 28*4882a593Smuzhiyun unsigned char oprtl; 29*4882a593Smuzhiyun unsigned char res1[3]; 30*4882a593Smuzhiyun unsigned char bprth; 31*4882a593Smuzhiyun unsigned char bprtl; 32*4882a593Smuzhiyun unsigned char gprt3; 33*4882a593Smuzhiyun unsigned char gprt2; 34*4882a593Smuzhiyun unsigned char gprt1; 35*4882a593Smuzhiyun unsigned char gprt0; 36*4882a593Smuzhiyun unsigned char res2[2]; 37*4882a593Smuzhiyun unsigned char prst; 38*4882a593Smuzhiyun unsigned char res3[0xfff0]; 39*4882a593Smuzhiyun unsigned char pgy_id; 40*4882a593Smuzhiyun unsigned char pgy_rev; 41*4882a593Smuzhiyun unsigned char pgy_outputs; 42*4882a593Smuzhiyun unsigned char pgy_eth; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define BFTICU_DIPSWITCH_MASK 0x0f 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * BFTICU FPGA iomap 49*4882a593Smuzhiyun * BFTICU is used on mgcoge and mgocge3ne 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun struct bfticu_iomap { 52*4882a593Smuzhiyun u8 xi_ena; /* General defect enable */ 53*4882a593Smuzhiyun u8 pack1[3]; 54*4882a593Smuzhiyun u8 en_csn; 55*4882a593Smuzhiyun u8 pack2; 56*4882a593Smuzhiyun u8 safe_mem; 57*4882a593Smuzhiyun u8 pack3; 58*4882a593Smuzhiyun u8 id; 59*4882a593Smuzhiyun u8 pack4; 60*4882a593Smuzhiyun u8 rev; 61*4882a593Smuzhiyun u8 build; 62*4882a593Smuzhiyun u8 p_frc; 63*4882a593Smuzhiyun u8 p_msk; 64*4882a593Smuzhiyun u8 pack5[2]; 65*4882a593Smuzhiyun u8 xg_int; 66*4882a593Smuzhiyun u8 pack6[15]; 67*4882a593Smuzhiyun u8 s_conf; 68*4882a593Smuzhiyun u8 pack7; 69*4882a593Smuzhiyun u8 dmx_conf12; 70*4882a593Smuzhiyun u8 pack8; 71*4882a593Smuzhiyun u8 s_clkslv; 72*4882a593Smuzhiyun u8 pack9[11]; 73*4882a593Smuzhiyun u8 d_conf; 74*4882a593Smuzhiyun u8 d_mask_ca; 75*4882a593Smuzhiyun u8 d_pll_del; 76*4882a593Smuzhiyun u8 pack10[16]; 77*4882a593Smuzhiyun u8 t_conf_ca; 78*4882a593Smuzhiyun u8 t_mask_ca; 79*4882a593Smuzhiyun u8 pack11[13]; 80*4882a593Smuzhiyun u8 m_def0; 81*4882a593Smuzhiyun u8 m_def1; 82*4882a593Smuzhiyun u8 m_def2; 83*4882a593Smuzhiyun u8 m_def3; 84*4882a593Smuzhiyun u8 m_def4; 85*4882a593Smuzhiyun u8 m_def5; 86*4882a593Smuzhiyun u8 m_def_trap0; 87*4882a593Smuzhiyun u8 m_def_trap1; 88*4882a593Smuzhiyun u8 m_def_trap2; 89*4882a593Smuzhiyun u8 m_def_trap3; 90*4882a593Smuzhiyun u8 m_def_trap4; 91*4882a593Smuzhiyun u8 m_def_trap5; 92*4882a593Smuzhiyun u8 m_mask_def0; 93*4882a593Smuzhiyun u8 m_mask_def1; 94*4882a593Smuzhiyun u8 m_mask_def2; 95*4882a593Smuzhiyun u8 m_mask_def3; 96*4882a593Smuzhiyun u8 m_mask_def4; 97*4882a593Smuzhiyun u8 m_mask_def5; 98*4882a593Smuzhiyun u8 m_def_mask0; 99*4882a593Smuzhiyun u8 m_def_mask1; 100*4882a593Smuzhiyun u8 m_def_mask2; 101*4882a593Smuzhiyun u8 m_def_mask3; 102*4882a593Smuzhiyun u8 m_def_mask4; 103*4882a593Smuzhiyun u8 m_def_mask5; 104*4882a593Smuzhiyun u8 m_def_pri; 105*4882a593Smuzhiyun u8 pack12[11]; 106*4882a593Smuzhiyun u8 hw_status; 107*4882a593Smuzhiyun u8 pack13; 108*4882a593Smuzhiyun u8 hw_control1; 109*4882a593Smuzhiyun u8 hw_control2; 110*4882a593Smuzhiyun u8 hw_control3; 111*4882a593Smuzhiyun u8 pack14[7]; 112*4882a593Smuzhiyun u8 led_on; /* Leds */ 113*4882a593Smuzhiyun u8 pack15; 114*4882a593Smuzhiyun u8 sfp_control; /* SFP modules */ 115*4882a593Smuzhiyun u8 pack16; 116*4882a593Smuzhiyun u8 alarm_control; /* Alarm output */ 117*4882a593Smuzhiyun u8 pack17; 118*4882a593Smuzhiyun u8 icps; /* ICN clock pulse shaping */ 119*4882a593Smuzhiyun u8 mswitch; /* Read mode switch */ 120*4882a593Smuzhiyun u8 pack18[6]; 121*4882a593Smuzhiyun u8 pb_dbug; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #if !defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET) 125*4882a593Smuzhiyun #define CONFIG_PIGGY_MAC_ADRESS_OFFSET 0 126*4882a593Smuzhiyun #endif 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun int ethernet_present(void); 129*4882a593Smuzhiyun int ivm_read_eeprom(unsigned char *buf, int len); 130*4882a593Smuzhiyun int ivm_analyze_eeprom(unsigned char *buf, int len); 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun int trigger_fpga_config(void); 133*4882a593Smuzhiyun int wait_for_fpga_config(void); 134*4882a593Smuzhiyun int fpga_reset(void); 135*4882a593Smuzhiyun int toggle_eeprom_spi_bus(void); 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun int get_testpin(void); 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun int set_km_env(void); 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */ 142*4882a593Smuzhiyun #define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000)) 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun int i2c_soft_read_pin(void); 145*4882a593Smuzhiyun int i2c_make_abort(void); 146*4882a593Smuzhiyun #endif /* __KEYMILE_COMMON_H */ 147