1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 3*4882a593Smuzhiyun */ 4*4882a593Smuzhiyun #include <common.h> 5*4882a593Smuzhiyun #include <twl4030.h> 6*4882a593Smuzhiyun #include <asm/io.h> 7*4882a593Smuzhiyun #include <asm/omap_mmc.h> 8*4882a593Smuzhiyun #include <asm/arch/mux.h> 9*4882a593Smuzhiyun #include <asm/arch/sys_proto.h> 10*4882a593Smuzhiyun #include <jffs2/load_kernel.h> 11*4882a593Smuzhiyun #include <linux/mtd/rawnand.h> 12*4882a593Smuzhiyun #include "igep00x0.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * Routine: set_muxconf_regs 18*4882a593Smuzhiyun * Description: Setting up the configuration Mux registers specific to the 19*4882a593Smuzhiyun * hardware. Many pins need to be moved from protect to primary 20*4882a593Smuzhiyun * mode. 21*4882a593Smuzhiyun */ set_muxconf_regs(void)22*4882a593Smuzhiyunvoid set_muxconf_regs(void) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun MUX_DEFAULT(); 25*4882a593Smuzhiyun } 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * Routine: board_init 29*4882a593Smuzhiyun * Description: Early hardware init. 30*4882a593Smuzhiyun */ board_init(void)31*4882a593Smuzhiyunint board_init(void) 32*4882a593Smuzhiyun { 33*4882a593Smuzhiyun int loops = 100; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* find out flash memory type, assume NAND first */ 36*4882a593Smuzhiyun gpmc_cs0_flash = MTD_DEV_TYPE_NAND; 37*4882a593Smuzhiyun gpmc_init(); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Issue a RESET and then READID */ 40*4882a593Smuzhiyun writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); 41*4882a593Smuzhiyun writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); 42*4882a593Smuzhiyun while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) 43*4882a593Smuzhiyun != NAND_STATUS_READY) { 44*4882a593Smuzhiyun udelay(1); 45*4882a593Smuzhiyun if (--loops == 0) { 46*4882a593Smuzhiyun gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; 47*4882a593Smuzhiyun gpmc_init(); /* reinitialize for OneNAND */ 48*4882a593Smuzhiyun break; 49*4882a593Smuzhiyun } 50*4882a593Smuzhiyun } 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* boot param addr */ 53*4882a593Smuzhiyun gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun return 0; 56*4882a593Smuzhiyun } 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #if defined(CONFIG_MMC) board_mmc_init(bd_t * bis)59*4882a593Smuzhiyunint board_mmc_init(bd_t *bis) 60*4882a593Smuzhiyun { 61*4882a593Smuzhiyun return omap_mmc_init(0, 0, 0, -1, -1); 62*4882a593Smuzhiyun } 63*4882a593Smuzhiyun board_mmc_power_init(void)64*4882a593Smuzhiyunvoid board_mmc_power_init(void) 65*4882a593Smuzhiyun { 66*4882a593Smuzhiyun twl4030_power_mmc_init(0); 67*4882a593Smuzhiyun } 68*4882a593Smuzhiyun #endif 69