1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2009-2012
3*4882a593Smuzhiyun * Wojciech Dubowik <wojciech.dubowik@neratec.com>
4*4882a593Smuzhiyun * Luka Perkov <luka@openwrt.org>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <miiphy.h>
11*4882a593Smuzhiyun #include <asm/arch/cpu.h>
12*4882a593Smuzhiyun #include <asm/arch/soc.h>
13*4882a593Smuzhiyun #include <asm/arch/mpp.h>
14*4882a593Smuzhiyun #include "iconnect.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
board_early_init_f(void)18*4882a593Smuzhiyun int board_early_init_f(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * default gpio configuration
22*4882a593Smuzhiyun * There are maximum 64 gpios controlled through 2 sets of registers
23*4882a593Smuzhiyun * the below configuration configures mainly initial LED status
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun mvebu_config_gpio(ICONNECT_OE_VAL_LOW,
26*4882a593Smuzhiyun ICONNECT_OE_VAL_HIGH,
27*4882a593Smuzhiyun ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* Multi-Purpose Pins Functionality configuration */
30*4882a593Smuzhiyun static const u32 kwmpp_config[] = {
31*4882a593Smuzhiyun MPP0_NF_IO2,
32*4882a593Smuzhiyun MPP1_NF_IO3,
33*4882a593Smuzhiyun MPP2_NF_IO4,
34*4882a593Smuzhiyun MPP3_NF_IO5,
35*4882a593Smuzhiyun MPP4_NF_IO6,
36*4882a593Smuzhiyun MPP5_NF_IO7,
37*4882a593Smuzhiyun MPP6_SYSRST_OUTn, /* Reset signal */
38*4882a593Smuzhiyun MPP7_GPO,
39*4882a593Smuzhiyun MPP8_TW_SDA, /* I2C */
40*4882a593Smuzhiyun MPP9_TW_SCK, /* I2C */
41*4882a593Smuzhiyun MPP10_UART0_TXD,
42*4882a593Smuzhiyun MPP11_UART0_RXD,
43*4882a593Smuzhiyun MPP12_GPO, /* Reset button */
44*4882a593Smuzhiyun MPP13_SD_CMD,
45*4882a593Smuzhiyun MPP14_SD_D0,
46*4882a593Smuzhiyun MPP15_SD_D1,
47*4882a593Smuzhiyun MPP16_SD_D2,
48*4882a593Smuzhiyun MPP17_SD_D3,
49*4882a593Smuzhiyun MPP18_NF_IO0,
50*4882a593Smuzhiyun MPP19_NF_IO1,
51*4882a593Smuzhiyun MPP20_GE1_0,
52*4882a593Smuzhiyun MPP21_GE1_1,
53*4882a593Smuzhiyun MPP22_GE1_2,
54*4882a593Smuzhiyun MPP23_GE1_3,
55*4882a593Smuzhiyun MPP24_GE1_4,
56*4882a593Smuzhiyun MPP25_GE1_5,
57*4882a593Smuzhiyun MPP26_GE1_6,
58*4882a593Smuzhiyun MPP27_GE1_7,
59*4882a593Smuzhiyun MPP28_GPIO,
60*4882a593Smuzhiyun MPP29_GPIO,
61*4882a593Smuzhiyun MPP30_GE1_10,
62*4882a593Smuzhiyun MPP31_GE1_11,
63*4882a593Smuzhiyun MPP32_GE1_12,
64*4882a593Smuzhiyun MPP33_GE1_13,
65*4882a593Smuzhiyun MPP34_GE1_14,
66*4882a593Smuzhiyun MPP35_GPIO, /* OTB button */
67*4882a593Smuzhiyun MPP36_AUDIO_SPDIFI,
68*4882a593Smuzhiyun MPP37_AUDIO_SPDIFO,
69*4882a593Smuzhiyun MPP38_GPIO,
70*4882a593Smuzhiyun MPP39_TDM_SPI_CS0,
71*4882a593Smuzhiyun MPP40_TDM_SPI_SCK,
72*4882a593Smuzhiyun MPP41_GPIO, /* LED brightness */
73*4882a593Smuzhiyun MPP42_GPIO, /* LED power (blue) */
74*4882a593Smuzhiyun MPP43_GPIO, /* LED power (red) */
75*4882a593Smuzhiyun MPP44_GPIO, /* LED USB 1 */
76*4882a593Smuzhiyun MPP45_GPIO, /* LED USB 2 */
77*4882a593Smuzhiyun MPP46_GPIO, /* LED USB 3 */
78*4882a593Smuzhiyun MPP47_GPIO, /* LED USB 4 */
79*4882a593Smuzhiyun MPP48_GPIO, /* LED OTB */
80*4882a593Smuzhiyun MPP49_GPIO,
81*4882a593Smuzhiyun 0
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun kirkwood_mpp_conf(kwmpp_config, NULL);
84*4882a593Smuzhiyun return 0;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
board_init(void)87*4882a593Smuzhiyun int board_init(void)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun /* adress of boot parameters */
90*4882a593Smuzhiyun gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun }
94