1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <asm/arch/device.h>
10*4882a593Smuzhiyun #include <asm/arch/quark.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /*
13*4882a593Smuzhiyun * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * We cannot use any public GPIO APIs in <asm-generic/gpio.h> to control this
16*4882a593Smuzhiyun * pin, as these APIs will eventually call into gpio_ich6_ofdata_to_platdata()
17*4882a593Smuzhiyun * in the Intel ICH6 GPIO driver where it calls PCI configuration space access
18*4882a593Smuzhiyun * APIs which will trigger PCI enumeration process.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Check <asm/arch-quark/quark.h> for more details.
21*4882a593Smuzhiyun */
board_assert_perst(void)22*4882a593Smuzhiyun void board_assert_perst(void)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun u32 base, port, val;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* retrieve the GPIO IO base */
27*4882a593Smuzhiyun qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
28*4882a593Smuzhiyun base = (base & 0xffff) & ~0x7f;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* enable the pin */
31*4882a593Smuzhiyun port = base + 0x20;
32*4882a593Smuzhiyun val = inl(port);
33*4882a593Smuzhiyun val |= (1 << 0);
34*4882a593Smuzhiyun outl(val, port);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* configure the pin as output */
37*4882a593Smuzhiyun port = base + 0x24;
38*4882a593Smuzhiyun val = inl(port);
39*4882a593Smuzhiyun val &= ~(1 << 0);
40*4882a593Smuzhiyun outl(val, port);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* pull it down (assert) */
43*4882a593Smuzhiyun port = base + 0x28;
44*4882a593Smuzhiyun val = inl(port);
45*4882a593Smuzhiyun val &= ~(1 << 0);
46*4882a593Smuzhiyun outl(val, port);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
board_deassert_perst(void)49*4882a593Smuzhiyun void board_deassert_perst(void)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun u32 base, port, val;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* retrieve the GPIO IO base */
54*4882a593Smuzhiyun qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
55*4882a593Smuzhiyun base = (base & 0xffff) & ~0x7f;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* pull it up (de-assert) */
58*4882a593Smuzhiyun port = base + 0x28;
59*4882a593Smuzhiyun val = inl(port);
60*4882a593Smuzhiyun val |= (1 << 0);
61*4882a593Smuzhiyun outl(val, port);
62*4882a593Smuzhiyun }
63