1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Imagination Technologies MIPSfpga platform code 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2016, Imagination Technologies Ltd. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <common.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* initialize the DDR Controller and PHY */ dram_init(void)17*4882a593Smuzhiyunint dram_init(void) 18*4882a593Smuzhiyun { 19*4882a593Smuzhiyun /* MIG IP block is smart and doesn't need SW 20*4882a593Smuzhiyun * to do any init */ 21*4882a593Smuzhiyun gd->ram_size = CONFIG_SYS_SDRAM_SIZE; /* in bytes */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun return 0; 24*4882a593Smuzhiyun } 25