1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Imagination Technologies 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __BOARD_BOSTON_REGS_H__ 8*4882a593Smuzhiyun #define __BOARD_BOSTON_REGS_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <asm/addrspace.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define BOSTON_PLAT_BASE CKSEG1ADDR(0x17ffd000) 13*4882a593Smuzhiyun #define BOSTON_LCD_BASE CKSEG1ADDR(0x17fff000) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Platform Register Definitions 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define BOSTON_PLAT_CORE_CL (BOSTON_PLAT_BASE + 0x04) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define BOSTON_PLAT_DDR3STAT (BOSTON_PLAT_BASE + 0x14) 21*4882a593Smuzhiyun # define BOSTON_PLAT_DDR3STAT_CALIB (1 << 2) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define BOSTON_PLAT_DDRCONF0 (BOSTON_PLAT_BASE + 0x38) 24*4882a593Smuzhiyun # define BOSTON_PLAT_DDRCONF0_SIZE (0xf << 0) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #endif /* __BOARD_BOSTON_REGS_H__ */ 27