1 /*
2 * (C) Copyright 2015 Linaro
3 * Peter Griffin <peter.griffin@linaro.org>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7 #include <common.h>
8 #include <dm.h>
9 #include <dm/platform_data/serial_pl01x.h>
10 #include <errno.h>
11 #include <malloc.h>
12 #include <netdev.h>
13 #include <asm/io.h>
14 #include <usb.h>
15 #include <power/hi6553_pmic.h>
16 #include <asm-generic/gpio.h>
17 #include <asm/arch/dwmmc.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/periph.h>
20 #include <asm/arch/pinmux.h>
21 #include <asm/arch/hi6220.h>
22 #include <asm/armv8/mmu.h>
23
24 /*TODO drop this table in favour of device tree */
25 static const struct hikey_gpio_platdata hi6220_gpio[] = {
26 { 0, HI6220_GPIO_BASE(0)},
27 { 1, HI6220_GPIO_BASE(1)},
28 { 2, HI6220_GPIO_BASE(2)},
29 { 3, HI6220_GPIO_BASE(3)},
30 { 4, HI6220_GPIO_BASE(4)},
31 { 5, HI6220_GPIO_BASE(5)},
32 { 6, HI6220_GPIO_BASE(6)},
33 { 7, HI6220_GPIO_BASE(7)},
34 { 8, HI6220_GPIO_BASE(8)},
35 { 9, HI6220_GPIO_BASE(9)},
36 { 10, HI6220_GPIO_BASE(10)},
37 { 11, HI6220_GPIO_BASE(11)},
38 { 12, HI6220_GPIO_BASE(12)},
39 { 13, HI6220_GPIO_BASE(13)},
40 { 14, HI6220_GPIO_BASE(14)},
41 { 15, HI6220_GPIO_BASE(15)},
42 { 16, HI6220_GPIO_BASE(16)},
43 { 17, HI6220_GPIO_BASE(17)},
44 { 18, HI6220_GPIO_BASE(18)},
45 { 19, HI6220_GPIO_BASE(19)},
46
47 };
48
49 U_BOOT_DEVICES(hi6220_gpios) = {
50 { "gpio_hi6220", &hi6220_gpio[0] },
51 { "gpio_hi6220", &hi6220_gpio[1] },
52 { "gpio_hi6220", &hi6220_gpio[2] },
53 { "gpio_hi6220", &hi6220_gpio[3] },
54 { "gpio_hi6220", &hi6220_gpio[4] },
55 { "gpio_hi6220", &hi6220_gpio[5] },
56 { "gpio_hi6220", &hi6220_gpio[6] },
57 { "gpio_hi6220", &hi6220_gpio[7] },
58 { "gpio_hi6220", &hi6220_gpio[8] },
59 { "gpio_hi6220", &hi6220_gpio[9] },
60 { "gpio_hi6220", &hi6220_gpio[10] },
61 { "gpio_hi6220", &hi6220_gpio[11] },
62 { "gpio_hi6220", &hi6220_gpio[12] },
63 { "gpio_hi6220", &hi6220_gpio[13] },
64 { "gpio_hi6220", &hi6220_gpio[14] },
65 { "gpio_hi6220", &hi6220_gpio[15] },
66 { "gpio_hi6220", &hi6220_gpio[16] },
67 { "gpio_hi6220", &hi6220_gpio[17] },
68 { "gpio_hi6220", &hi6220_gpio[18] },
69 { "gpio_hi6220", &hi6220_gpio[19] },
70 };
71
72 DECLARE_GLOBAL_DATA_PTR;
73
74 #if !CONFIG_IS_ENABLED(OF_CONTROL)
75
76 static const struct pl01x_serial_platdata serial_platdata = {
77 #if CONFIG_CONS_INDEX == 1
78 .base = HI6220_UART0_BASE,
79 #elif CONFIG_CONS_INDEX == 4
80 .base = HI6220_UART3_BASE,
81 #else
82 #error "Unsupported console index value."
83 #endif
84 .type = TYPE_PL011,
85 .clock = 19200000
86 };
87
88 U_BOOT_DEVICE(hikey_seriala) = {
89 .name = "serial_pl01x",
90 .platdata = &serial_platdata,
91 };
92 #endif
93
94 static struct mm_region hikey_mem_map[] = {
95 {
96 .virt = 0x0UL,
97 .phys = 0x0UL,
98 .size = 0x80000000UL,
99 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
100 PTE_BLOCK_INNER_SHARE
101 }, {
102 .virt = 0x80000000UL,
103 .phys = 0x80000000UL,
104 .size = 0x80000000UL,
105 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
106 PTE_BLOCK_NON_SHARE |
107 PTE_BLOCK_PXN | PTE_BLOCK_UXN
108 }, {
109 /* List terminator */
110 0,
111 }
112 };
113
114 struct mm_region *mem_map = hikey_mem_map;
115
116 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_uart_init(void)117 int board_uart_init(void)
118 {
119 switch (CONFIG_CONS_INDEX) {
120 case 1:
121 hi6220_pinmux_config(PERIPH_ID_UART0);
122 break;
123 case 4:
124 hi6220_pinmux_config(PERIPH_ID_UART3);
125 break;
126 default:
127 debug("%s: Unsupported UART selected\n", __func__);
128 return -1;
129 }
130
131 return 0;
132 }
133
board_early_init_f(void)134 int board_early_init_f(void)
135 {
136 board_uart_init();
137 return 0;
138 }
139 #endif
140
141 struct peri_sc_periph_regs *peri_sc =
142 (struct peri_sc_periph_regs *)HI6220_PERI_BASE;
143
144 struct alwayson_sc_regs *ao_sc =
145 (struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
146
147 /* status offset from enable reg */
148 #define STAT_EN_OFF 0x2
149
hi6220_clk_enable(u32 bitfield,unsigned int * clk_base)150 void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
151 {
152 uint32_t data;
153
154 data = readl(clk_base);
155 data |= bitfield;
156
157 writel(bitfield, clk_base);
158 do {
159 data = readl(clk_base + STAT_EN_OFF);
160 } while ((data & bitfield) == 0);
161 }
162
163 /* status offset from disable reg */
164 #define STAT_DIS_OFF 0x1
165
hi6220_clk_disable(u32 bitfield,unsigned int * clk_base)166 void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
167 {
168 uint32_t data;
169
170 data = readl(clk_base);
171 data |= bitfield;
172
173 writel(data, clk_base);
174 do {
175 data = readl(clk_base + STAT_DIS_OFF);
176 } while (data & bitfield);
177 }
178
179 #define EYE_PATTERN 0x70533483
180
board_usb_init(int index,enum usb_init_type init)181 int board_usb_init(int index, enum usb_init_type init)
182 {
183 unsigned int data;
184
185 /* enable USB clock */
186 hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
187
188 /* take usb IPs out of reset */
189 writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
190 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
191 &peri_sc->rst0_dis);
192 do {
193 data = readl(&peri_sc->rst0_stat);
194 data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
195 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
196 } while (data);
197
198 /*CTRL 5*/
199 data = readl(&peri_sc->ctrl5);
200 data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
201 data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
202 data |= 0x300;
203 writel(data, &peri_sc->ctrl5);
204
205 /*CTRL 4*/
206
207 /* configure USB PHY */
208 data = readl(&peri_sc->ctrl4);
209
210 /* make PHY out of low power mode */
211 data &= ~PERI_CTRL4_PICO_SIDDQ;
212 data &= ~PERI_CTRL4_PICO_OGDISABLE;
213 data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
214 writel(data, &peri_sc->ctrl4);
215
216 writel(EYE_PATTERN, &peri_sc->ctrl8);
217
218 mdelay(5);
219 return 0;
220 }
221
config_sd_carddetect(void)222 static int config_sd_carddetect(void)
223 {
224 int ret;
225
226 /* configure GPIO8 as nopull */
227 writel(0, 0xf8001830);
228
229 gpio_request(8, "SD CD");
230
231 gpio_direction_input(8);
232 ret = gpio_get_value(8);
233
234 if (!ret) {
235 printf("%s: SD card present\n", __func__);
236 return 1;
237 }
238
239 printf("%s: SD card not present\n", __func__);
240 return 0;
241 }
242
243
mmc1_init_pll(void)244 static void mmc1_init_pll(void)
245 {
246 uint32_t data;
247
248 /* select SYSPLL as the source of MMC1 */
249 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
250 writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
251 do {
252 data = readl(&peri_sc->clk0_sel);
253 } while (!(data & (1 << 11)));
254
255 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
256 writel(1 << 30, &peri_sc->clk0_sel);
257 do {
258 data = readl(&peri_sc->clk0_sel);
259 } while (data & (1 << 14));
260
261 hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
262
263 hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
264
265 do {
266 /* 1.2GHz / 50 = 24MHz */
267 writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
268 data = readl(&peri_sc->clkcfg8bit2);
269 } while ((data & 0x31) != 0x31);
270 }
271
mmc1_reset_clk(void)272 static void mmc1_reset_clk(void)
273 {
274 unsigned int data;
275
276 /* disable mmc1 bus clock */
277 hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
278
279 /* enable mmc1 bus clock */
280 hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
281
282 /* reset mmc1 clock domain */
283 writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
284
285 /* bypass mmc1 clock phase */
286 data = readl(&peri_sc->ctrl2);
287 data |= 3 << 2;
288 writel(data, &peri_sc->ctrl2);
289
290 /* disable low power */
291 data = readl(&peri_sc->ctrl13);
292 data |= 1 << 4;
293 writel(data, &peri_sc->ctrl13);
294 do {
295 data = readl(&peri_sc->rst0_stat);
296 } while (!(data & PERI_RST0_MMC1));
297
298 /* unreset mmc1 clock domain */
299 writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
300 do {
301 data = readl(&peri_sc->rst0_stat);
302 } while (data & PERI_RST0_MMC1);
303 }
304
mmc0_reset_clk(void)305 static void mmc0_reset_clk(void)
306 {
307 unsigned int data;
308
309 /* disable mmc0 bus clock */
310 hi6220_clk_disable(PERI_CLK0_MMC0, &peri_sc->clk0_dis);
311
312 /* enable mmc0 bus clock */
313 hi6220_clk_enable(PERI_CLK0_MMC0, &peri_sc->clk0_en);
314
315 /* reset mmc0 clock domain */
316 writel(PERI_RST0_MMC0, &peri_sc->rst0_en);
317
318 /* bypass mmc0 clock phase */
319 data = readl(&peri_sc->ctrl2);
320 data |= 3;
321 writel(data, &peri_sc->ctrl2);
322
323 /* disable low power */
324 data = readl(&peri_sc->ctrl13);
325 data |= 1 << 3;
326 writel(data, &peri_sc->ctrl13);
327 do {
328 data = readl(&peri_sc->rst0_stat);
329 } while (!(data & PERI_RST0_MMC0));
330
331 /* unreset mmc0 clock domain */
332 writel(PERI_RST0_MMC0, &peri_sc->rst0_dis);
333 do {
334 data = readl(&peri_sc->rst0_stat);
335 } while (data & PERI_RST0_MMC0);
336 }
337
338
339 /* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
hi6220_pmussi_init(void)340 static void hi6220_pmussi_init(void)
341 {
342 uint32_t data;
343
344 /* Take PMUSSI out of reset */
345 writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
346 &ao_sc->rst4_dis);
347 do {
348 data = readl(&ao_sc->rst4_stat);
349 } while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
350
351 /* set PMU SSI clock latency for read operation */
352 data = readl(&ao_sc->mcu_subsys_ctrl3);
353 data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
354 data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
355 writel(data, &ao_sc->mcu_subsys_ctrl3);
356
357 /* enable PMUSSI clock */
358 data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
359 ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
360
361 hi6220_clk_enable(data, &ao_sc->clk5_en);
362
363 /* Output high to PMIC on PWR_HOLD_GPIO0_0 */
364 gpio_request(0, "PWR_HOLD_GPIO0_0");
365 gpio_direction_output(0, 1);
366 }
367
misc_init_r(void)368 int misc_init_r(void)
369 {
370 return 0;
371 }
372
board_init(void)373 int board_init(void)
374 {
375 return 0;
376 }
377
378 #ifdef CONFIG_MMC
379
init_dwmmc(void)380 static int init_dwmmc(void)
381 {
382 int ret = 0;
383
384 #ifdef CONFIG_MMC_DW
385
386 /* mmc0 pll is already configured by ATF */
387 mmc0_reset_clk();
388 ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
389 if (ret)
390 printf("%s: Error configuring pinmux for eMMC (%d)\n"
391 , __func__, ret);
392
393 ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
394 if (ret)
395 printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
396
397
398 /* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
399 mmc1_init_pll();
400 mmc1_reset_clk();
401
402 ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
403 if (ret)
404 printf("%s: Error configuring pinmux for eMMC (%d)\n"
405 , __func__, ret);
406
407 config_sd_carddetect();
408
409 ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
410 if (ret)
411 printf("%s: Error adding SD port (%d)\n", __func__, ret);
412
413 #endif
414 return ret;
415 }
416
417 /* setup board specific PMIC */
power_init_board(void)418 int power_init_board(void)
419 {
420 /* init the hi6220 pmussi ip */
421 hi6220_pmussi_init();
422
423 power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
424
425 return 0;
426 }
427
board_mmc_init(bd_t * bis)428 int board_mmc_init(bd_t *bis)
429 {
430 int ret;
431
432 /* add the eMMC and sd ports */
433 ret = init_dwmmc();
434
435 if (ret)
436 debug("init_dwmmc failed\n");
437
438 return ret;
439 }
440 #endif
441
dram_init(void)442 int dram_init(void)
443 {
444 gd->ram_size = PHYS_SDRAM_1_SIZE;
445 return 0;
446 }
447
dram_init_banksize(void)448 int dram_init_banksize(void)
449 {
450 /*
451 * Reserve regions below from DT memory node (which gets generated
452 * by U-Boot from the dram banks in arch_fixup_fdt() before booting
453 * the kernel. This will then match the kernel hikey dts memory node.
454 *
455 * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
456 * 0x05f0,1000 - 0x05f0,1fff: Reboot reason
457 * 0x06df,f000 - 0x06df,ffff: Mailbox message data
458 * 0x0740,f000 - 0x0740,ffff: MCU firmware section
459 * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
460 * 0x3e00,0000 - 0x3fff,ffff: OP-TEE
461 */
462
463 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
464 gd->bd->bi_dram[0].size = 0x05e00000;
465
466 gd->bd->bi_dram[1].start = 0x05f00000;
467 gd->bd->bi_dram[1].size = 0x00001000;
468
469 gd->bd->bi_dram[2].start = 0x05f02000;
470 gd->bd->bi_dram[2].size = 0x00efd000;
471
472 gd->bd->bi_dram[3].start = 0x06e00000;
473 gd->bd->bi_dram[3].size = 0x0060f000;
474
475 gd->bd->bi_dram[4].start = 0x07410000;
476 gd->bd->bi_dram[4].size = 0x1aaf0000;
477
478 gd->bd->bi_dram[5].start = 0x22000000;
479 gd->bd->bi_dram[5].size = 0x1c000000;
480
481 return 0;
482 }
483
reset_cpu(ulong addr)484 void reset_cpu(ulong addr)
485 {
486 writel(0x48698284, &ao_sc->stat0);
487 wfi();
488 }
489