1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Muxing for Gumstix Pepper and AM335x-based boards
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
10*4882a593Smuzhiyun #include <asm/arch/hardware.h>
11*4882a593Smuzhiyun #include <asm/arch/mux.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <i2c.h>
14*4882a593Smuzhiyun #include "board.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static struct module_pin_mux uart0_pin_mux[] = {
17*4882a593Smuzhiyun {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
18*4882a593Smuzhiyun {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
19*4882a593Smuzhiyun {-1},
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static struct module_pin_mux mmc0_pin_mux[] = {
23*4882a593Smuzhiyun {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
24*4882a593Smuzhiyun {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
25*4882a593Smuzhiyun {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
26*4882a593Smuzhiyun {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
27*4882a593Smuzhiyun {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
28*4882a593Smuzhiyun {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
29*4882a593Smuzhiyun {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
30*4882a593Smuzhiyun {-1},
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static struct module_pin_mux i2c0_pin_mux[] = {
34*4882a593Smuzhiyun /* I2C_DATA */
35*4882a593Smuzhiyun {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
36*4882a593Smuzhiyun /* I2C_SCLK */
37*4882a593Smuzhiyun {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
38*4882a593Smuzhiyun {-1},
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun static struct module_pin_mux rgmii1_pin_mux[] = {
42*4882a593Smuzhiyun {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
43*4882a593Smuzhiyun {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
44*4882a593Smuzhiyun {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
45*4882a593Smuzhiyun {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
46*4882a593Smuzhiyun {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
47*4882a593Smuzhiyun {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
48*4882a593Smuzhiyun {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
49*4882a593Smuzhiyun {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
50*4882a593Smuzhiyun {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
51*4882a593Smuzhiyun {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
52*4882a593Smuzhiyun {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
53*4882a593Smuzhiyun {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
54*4882a593Smuzhiyun {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
55*4882a593Smuzhiyun {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
56*4882a593Smuzhiyun {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */
57*4882a593Smuzhiyun {OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */
58*4882a593Smuzhiyun {OFFSET(xdma_event_intr1), MODE(3)},
59*4882a593Smuzhiyun {-1},
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
enable_uart0_pin_mux(void)62*4882a593Smuzhiyun void enable_uart0_pin_mux(void)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun configure_module_pin_mux(uart0_pin_mux);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
enable_i2c0_pin_mux(void)67*4882a593Smuzhiyun void enable_i2c0_pin_mux(void)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun configure_module_pin_mux(i2c0_pin_mux);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /*
73*4882a593Smuzhiyun * Do board-specific muxes.
74*4882a593Smuzhiyun */
enable_board_pin_mux(void)75*4882a593Smuzhiyun void enable_board_pin_mux(void)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun /* I2C0 */
78*4882a593Smuzhiyun configure_module_pin_mux(i2c0_pin_mux);
79*4882a593Smuzhiyun /* SD Card */
80*4882a593Smuzhiyun configure_module_pin_mux(mmc0_pin_mux);
81*4882a593Smuzhiyun /* Ethernet pinmux. */
82*4882a593Smuzhiyun configure_module_pin_mux(rgmii1_pin_mux);
83*4882a593Smuzhiyun }
84