1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2010 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4*4882a593Smuzhiyun * Timur Tabi <timur@freescale.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun #include <asm/mmu.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 13*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 14*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 15*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 16*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 17*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 18*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 20*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 21*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 23*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 24*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 25*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 26*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 27*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 28*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* TLB 1 */ 31*4882a593Smuzhiyun /* *I*** - Covers boot page */ 32*4882a593Smuzhiyun SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 33*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, 34*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 1), 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* *I*G* - CCSRBAR */ 37*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 38*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 39*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_1M, 1), 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* *I*G* - eLBC */ 42*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_ELBC_BASE, CONFIG_SYS_ELBC_BASE_PHYS, 43*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 44*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_1M, 1), 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #if defined(CONFIG_TRAILBLAZER) 47*4882a593Smuzhiyun /* *I*G - L2SRAM */ 48*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 49*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 50*4882a593Smuzhiyun 0, 9, BOOKE_PAGESZ_256K, 1), 51*4882a593Smuzhiyun #else 52*4882a593Smuzhiyun /* *I*G* - PCI */ 53*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 54*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 55*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_256M, 1), 56*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, 57*4882a593Smuzhiyun CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, 58*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 59*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_256M, 1), 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* *I*G* - PCI I/O */ 62*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 63*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 64*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_256K, 1), 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #ifdef CONFIG_SYS_RAMBOOT 67*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 68*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 69*4882a593Smuzhiyun 0, 6, BOOKE_PAGESZ_1G, 1), 70*4882a593Smuzhiyun #endif 71*4882a593Smuzhiyun #endif 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 75