1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2010-2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Authors: Timur Tabi <timur@freescale.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * FSL DIU Framebuffer driver
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <command.h>
12*4882a593Smuzhiyun #include <linux/ctype.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun #include <stdio_dev.h>
15*4882a593Smuzhiyun #include <video_fb.h>
16*4882a593Smuzhiyun #include <fsl_diu_fb.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define PMUXCR_ELBCDIU_MASK 0xc0000000
19*4882a593Smuzhiyun #define PMUXCR_ELBCDIU_NOR16 0x80000000
20*4882a593Smuzhiyun #define PMUXCR_ELBCDIU_DIU 0x40000000
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun * DIU Area Descriptor
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * Note that we need to byte-swap the value before it's written to the AD
26*4882a593Smuzhiyun * register. So even though the registers don't look like they're in the same
27*4882a593Smuzhiyun * bit positions as they are on the MPC8610, the same value is written to the
28*4882a593Smuzhiyun * AD register on the MPC8610 and on the P1022.
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun #define AD_BYTE_F 0x10000000
31*4882a593Smuzhiyun #define AD_ALPHA_C_SHIFT 25
32*4882a593Smuzhiyun #define AD_BLUE_C_SHIFT 23
33*4882a593Smuzhiyun #define AD_GREEN_C_SHIFT 21
34*4882a593Smuzhiyun #define AD_RED_C_SHIFT 19
35*4882a593Smuzhiyun #define AD_PIXEL_S_SHIFT 16
36*4882a593Smuzhiyun #define AD_COMP_3_SHIFT 12
37*4882a593Smuzhiyun #define AD_COMP_2_SHIFT 8
38*4882a593Smuzhiyun #define AD_COMP_1_SHIFT 4
39*4882a593Smuzhiyun #define AD_COMP_0_SHIFT 0
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun * Variables used by the DIU/LBC switching code. It's safe to makes these
43*4882a593Smuzhiyun * global, because the DIU requires DDR, so we'll only run this code after
44*4882a593Smuzhiyun * relocation.
45*4882a593Smuzhiyun */
46*4882a593Smuzhiyun static u32 pmuxcr;
47*4882a593Smuzhiyun
diu_set_pixel_clock(unsigned int pixclock)48*4882a593Smuzhiyun void diu_set_pixel_clock(unsigned int pixclock)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
51*4882a593Smuzhiyun unsigned long speed_ccb, temp;
52*4882a593Smuzhiyun u32 pixval;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun speed_ccb = get_bus_freq(0);
55*4882a593Smuzhiyun temp = 1000000000 / pixclock;
56*4882a593Smuzhiyun temp *= 1000;
57*4882a593Smuzhiyun pixval = speed_ccb / temp;
58*4882a593Smuzhiyun debug("DIU pixval = %u\n", pixval);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Modify PXCLK in GUTS CLKDVDR */
61*4882a593Smuzhiyun temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
62*4882a593Smuzhiyun out_be32(&gur->clkdvdr, temp); /* turn off clock */
63*4882a593Smuzhiyun out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
platform_diu_init(unsigned int xres,unsigned int yres,const char * port)66*4882a593Smuzhiyun int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
69*4882a593Smuzhiyun u32 pixel_format;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
72*4882a593Smuzhiyun (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
73*4882a593Smuzhiyun (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
74*4882a593Smuzhiyun (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
75*4882a593Smuzhiyun (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun printf("DIU: Switching to %ux%u\n", xres, yres);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
80*4882a593Smuzhiyun clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
81*4882a593Smuzhiyun pmuxcr = in_be32(&gur->pmuxcr);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return fsl_diu_init(xres, yres, pixel_format, 0);
84*4882a593Smuzhiyun }
85