1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2010
3*4882a593Smuzhiyun * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <miiphy.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun struct io_bb_pinset {
14*4882a593Smuzhiyun int mdio;
15*4882a593Smuzhiyun int mdc;
16*4882a593Smuzhiyun };
17*4882a593Smuzhiyun
io_bb_mii_init(struct bb_miiphy_bus * bus)18*4882a593Smuzhiyun static int io_bb_mii_init(struct bb_miiphy_bus *bus)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun return 0;
21*4882a593Smuzhiyun }
22*4882a593Smuzhiyun
io_bb_mdio_active(struct bb_miiphy_bus * bus)23*4882a593Smuzhiyun static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun struct io_bb_pinset *pins = bus->priv;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun out_be32((void *)GPIO0_TCR,
28*4882a593Smuzhiyun in_be32((void *)GPIO0_TCR) | pins->mdio);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun return 0;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
io_bb_mdio_tristate(struct bb_miiphy_bus * bus)33*4882a593Smuzhiyun static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun struct io_bb_pinset *pins = bus->priv;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun out_be32((void *)GPIO0_TCR,
38*4882a593Smuzhiyun in_be32((void *)GPIO0_TCR) & ~pins->mdio);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
io_bb_set_mdio(struct bb_miiphy_bus * bus,int v)43*4882a593Smuzhiyun static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun struct io_bb_pinset *pins = bus->priv;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun if (v)
48*4882a593Smuzhiyun out_be32((void *)GPIO0_OR,
49*4882a593Smuzhiyun in_be32((void *)GPIO0_OR) | pins->mdio);
50*4882a593Smuzhiyun else
51*4882a593Smuzhiyun out_be32((void *)GPIO0_OR,
52*4882a593Smuzhiyun in_be32((void *)GPIO0_OR) & ~pins->mdio);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return 0;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
io_bb_get_mdio(struct bb_miiphy_bus * bus,int * v)57*4882a593Smuzhiyun static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct io_bb_pinset *pins = bus->priv;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return 0;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
io_bb_set_mdc(struct bb_miiphy_bus * bus,int v)66*4882a593Smuzhiyun static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct io_bb_pinset *pins = bus->priv;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if (v)
71*4882a593Smuzhiyun out_be32((void *)GPIO0_OR,
72*4882a593Smuzhiyun in_be32((void *)GPIO0_OR) | pins->mdc);
73*4882a593Smuzhiyun else
74*4882a593Smuzhiyun out_be32((void *)GPIO0_OR,
75*4882a593Smuzhiyun in_be32((void *)GPIO0_OR) & ~pins->mdc);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
io_bb_delay(struct bb_miiphy_bus * bus)80*4882a593Smuzhiyun static int io_bb_delay(struct bb_miiphy_bus *bus)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun udelay(1);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return 0;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun struct io_bb_pinset io_bb_pinsets[] = {
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun .mdio = CONFIG_SYS_MDIO_PIN,
90*4882a593Smuzhiyun .mdc = CONFIG_SYS_MDC_PIN,
91*4882a593Smuzhiyun },
92*4882a593Smuzhiyun #ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun .mdio = CONFIG_SYS_MDIO1_PIN,
95*4882a593Smuzhiyun .mdc = CONFIG_SYS_MDC1_PIN,
96*4882a593Smuzhiyun },
97*4882a593Smuzhiyun #endif
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun struct bb_miiphy_bus bb_miiphy_buses[] = {
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun .name = CONFIG_SYS_GBIT_MII_BUSNAME,
103*4882a593Smuzhiyun .init = io_bb_mii_init,
104*4882a593Smuzhiyun .mdio_active = io_bb_mdio_active,
105*4882a593Smuzhiyun .mdio_tristate = io_bb_mdio_tristate,
106*4882a593Smuzhiyun .set_mdio = io_bb_set_mdio,
107*4882a593Smuzhiyun .get_mdio = io_bb_get_mdio,
108*4882a593Smuzhiyun .set_mdc = io_bb_set_mdc,
109*4882a593Smuzhiyun .delay = io_bb_delay,
110*4882a593Smuzhiyun .priv = &io_bb_pinsets[0],
111*4882a593Smuzhiyun },
112*4882a593Smuzhiyun #ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun .name = CONFIG_SYS_GBIT_MII1_BUSNAME,
115*4882a593Smuzhiyun .init = io_bb_mii_init,
116*4882a593Smuzhiyun .mdio_active = io_bb_mdio_active,
117*4882a593Smuzhiyun .mdio_tristate = io_bb_mdio_tristate,
118*4882a593Smuzhiyun .set_mdio = io_bb_set_mdio,
119*4882a593Smuzhiyun .get_mdio = io_bb_get_mdio,
120*4882a593Smuzhiyun .set_mdc = io_bb_set_mdc,
121*4882a593Smuzhiyun .delay = io_bb_delay,
122*4882a593Smuzhiyun .priv = &io_bb_pinsets[1],
123*4882a593Smuzhiyun },
124*4882a593Smuzhiyun #endif
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
128*4882a593Smuzhiyun sizeof(bb_miiphy_buses[0]);
129