1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2014
3*4882a593Smuzhiyun * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <gdsys_fpga.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun enum {
13*4882a593Smuzhiyun UNITTYPE_MAIN_SERVER = 0,
14*4882a593Smuzhiyun UNITTYPE_MAIN_USER = 1,
15*4882a593Smuzhiyun UNITTYPE_VIDEO_SERVER = 2,
16*4882a593Smuzhiyun UNITTYPE_VIDEO_USER = 3,
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun enum {
20*4882a593Smuzhiyun UNITTYPEPCB_DVI = 0,
21*4882a593Smuzhiyun UNITTYPEPCB_DP_165 = 1,
22*4882a593Smuzhiyun UNITTYPEPCB_DP_300 = 2,
23*4882a593Smuzhiyun UNITTYPEPCB_HDMI = 3,
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun enum {
27*4882a593Smuzhiyun COMPRESSION_NONE = 0,
28*4882a593Smuzhiyun COMPRESSION_TYPE_1 = 1,
29*4882a593Smuzhiyun COMPRESSION_TYPE_1_2 = 3,
30*4882a593Smuzhiyun COMPRESSION_TYPE_1_2_3 = 7,
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun enum {
34*4882a593Smuzhiyun AUDIO_NONE = 0,
35*4882a593Smuzhiyun AUDIO_TX = 1,
36*4882a593Smuzhiyun AUDIO_RX = 2,
37*4882a593Smuzhiyun AUDIO_RXTX = 3,
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun enum {
41*4882a593Smuzhiyun SYSCLK_147456 = 0,
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun enum {
45*4882a593Smuzhiyun RAM_DDR2_32 = 0,
46*4882a593Smuzhiyun RAM_DDR3_32 = 1,
47*4882a593Smuzhiyun RAM_DDR3_48 = 2,
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun enum {
51*4882a593Smuzhiyun CARRIER_SPEED_1G = 0,
52*4882a593Smuzhiyun CARRIER_SPEED_2_5G = 1,
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
ioep_fpga_has_osd(unsigned int fpga)55*4882a593Smuzhiyun bool ioep_fpga_has_osd(unsigned int fpga)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun u16 fpga_features;
58*4882a593Smuzhiyun unsigned feature_osd;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun FPGA_GET_REG(0, fpga_features, &fpga_features);
61*4882a593Smuzhiyun feature_osd = fpga_features & (1<<11);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return feature_osd;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
ioep_fpga_print_info(unsigned int fpga)66*4882a593Smuzhiyun void ioep_fpga_print_info(unsigned int fpga)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun u16 versions;
69*4882a593Smuzhiyun u16 fpga_version;
70*4882a593Smuzhiyun u16 fpga_features;
71*4882a593Smuzhiyun unsigned unit_type;
72*4882a593Smuzhiyun unsigned unit_type_pcb_video;
73*4882a593Smuzhiyun unsigned feature_compression;
74*4882a593Smuzhiyun unsigned feature_osd;
75*4882a593Smuzhiyun unsigned feature_audio;
76*4882a593Smuzhiyun unsigned feature_sysclock;
77*4882a593Smuzhiyun unsigned feature_ramconfig;
78*4882a593Smuzhiyun unsigned feature_carrier_speed;
79*4882a593Smuzhiyun unsigned feature_carriers;
80*4882a593Smuzhiyun unsigned feature_video_channels;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun FPGA_GET_REG(fpga, versions, &versions);
83*4882a593Smuzhiyun FPGA_GET_REG(fpga, fpga_version, &fpga_version);
84*4882a593Smuzhiyun FPGA_GET_REG(fpga, fpga_features, &fpga_features);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun unit_type = (versions & 0xf000) >> 12;
87*4882a593Smuzhiyun unit_type_pcb_video = (versions & 0x01c0) >> 6;
88*4882a593Smuzhiyun feature_compression = (fpga_features & 0xe000) >> 13;
89*4882a593Smuzhiyun feature_osd = fpga_features & (1<<11);
90*4882a593Smuzhiyun feature_audio = (fpga_features & 0x0600) >> 9;
91*4882a593Smuzhiyun feature_sysclock = (fpga_features & 0x0180) >> 7;
92*4882a593Smuzhiyun feature_ramconfig = (fpga_features & 0x0060) >> 5;
93*4882a593Smuzhiyun feature_carrier_speed = fpga_features & (1<<4);
94*4882a593Smuzhiyun feature_carriers = (fpga_features & 0x000c) >> 2;
95*4882a593Smuzhiyun feature_video_channels = fpga_features & 0x0003;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun switch (unit_type) {
98*4882a593Smuzhiyun case UNITTYPE_MAIN_SERVER:
99*4882a593Smuzhiyun case UNITTYPE_MAIN_USER:
100*4882a593Smuzhiyun printf("Mainchannel");
101*4882a593Smuzhiyun break;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun case UNITTYPE_VIDEO_SERVER:
104*4882a593Smuzhiyun case UNITTYPE_VIDEO_USER:
105*4882a593Smuzhiyun printf("Videochannel");
106*4882a593Smuzhiyun break;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun default:
109*4882a593Smuzhiyun printf("UnitType %d(not supported)", unit_type);
110*4882a593Smuzhiyun break;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun switch (unit_type) {
114*4882a593Smuzhiyun case UNITTYPE_MAIN_SERVER:
115*4882a593Smuzhiyun case UNITTYPE_VIDEO_SERVER:
116*4882a593Smuzhiyun printf(" Server");
117*4882a593Smuzhiyun if (versions & (1<<4))
118*4882a593Smuzhiyun printf(" UC");
119*4882a593Smuzhiyun break;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun case UNITTYPE_MAIN_USER:
122*4882a593Smuzhiyun case UNITTYPE_VIDEO_USER:
123*4882a593Smuzhiyun printf(" User");
124*4882a593Smuzhiyun break;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun default:
127*4882a593Smuzhiyun break;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun if (versions & (1<<5))
131*4882a593Smuzhiyun printf(" Fiber");
132*4882a593Smuzhiyun else
133*4882a593Smuzhiyun printf(" CAT");
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun switch (unit_type_pcb_video) {
136*4882a593Smuzhiyun case UNITTYPEPCB_DVI:
137*4882a593Smuzhiyun printf(" DVI,");
138*4882a593Smuzhiyun break;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun case UNITTYPEPCB_DP_165:
141*4882a593Smuzhiyun printf(" DP 165MPix/s,");
142*4882a593Smuzhiyun break;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun case UNITTYPEPCB_DP_300:
145*4882a593Smuzhiyun printf(" DP 300MPix/s,");
146*4882a593Smuzhiyun break;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun case UNITTYPEPCB_HDMI:
149*4882a593Smuzhiyun printf(" HDMI,");
150*4882a593Smuzhiyun break;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun printf(" FPGA V %d.%02d\n features:",
154*4882a593Smuzhiyun fpga_version / 100, fpga_version % 100);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun switch (feature_compression) {
158*4882a593Smuzhiyun case COMPRESSION_NONE:
159*4882a593Smuzhiyun printf(" no compression");
160*4882a593Smuzhiyun break;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun case COMPRESSION_TYPE_1:
163*4882a593Smuzhiyun printf(" compression type1(delta)");
164*4882a593Smuzhiyun break;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun case COMPRESSION_TYPE_1_2:
167*4882a593Smuzhiyun printf(" compression type1(delta), type2(inline)");
168*4882a593Smuzhiyun break;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun case COMPRESSION_TYPE_1_2_3:
171*4882a593Smuzhiyun printf(" compression type1(delta), type2(inline), type3(intempo)");
172*4882a593Smuzhiyun break;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun default:
175*4882a593Smuzhiyun printf(" compression %d(not supported)", feature_compression);
176*4882a593Smuzhiyun break;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun printf(", %sosd", feature_osd ? "" : "no ");
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun switch (feature_audio) {
182*4882a593Smuzhiyun case AUDIO_NONE:
183*4882a593Smuzhiyun printf(", no audio");
184*4882a593Smuzhiyun break;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun case AUDIO_TX:
187*4882a593Smuzhiyun printf(", audio tx");
188*4882a593Smuzhiyun break;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun case AUDIO_RX:
191*4882a593Smuzhiyun printf(", audio rx");
192*4882a593Smuzhiyun break;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun case AUDIO_RXTX:
195*4882a593Smuzhiyun printf(", audio rx+tx");
196*4882a593Smuzhiyun break;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun default:
199*4882a593Smuzhiyun printf(", audio %d(not supported)", feature_audio);
200*4882a593Smuzhiyun break;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun puts(",\n ");
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun switch (feature_sysclock) {
206*4882a593Smuzhiyun case SYSCLK_147456:
207*4882a593Smuzhiyun printf("clock 147.456 MHz");
208*4882a593Smuzhiyun break;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun default:
211*4882a593Smuzhiyun printf("clock %d(not supported)", feature_sysclock);
212*4882a593Smuzhiyun break;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun switch (feature_ramconfig) {
216*4882a593Smuzhiyun case RAM_DDR2_32:
217*4882a593Smuzhiyun printf(", RAM 32 bit DDR2");
218*4882a593Smuzhiyun break;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun case RAM_DDR3_32:
221*4882a593Smuzhiyun printf(", RAM 32 bit DDR3");
222*4882a593Smuzhiyun break;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun case RAM_DDR3_48:
225*4882a593Smuzhiyun printf(", RAM 48 bit DDR3");
226*4882a593Smuzhiyun break;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun default:
229*4882a593Smuzhiyun printf(", RAM %d(not supported)", feature_ramconfig);
230*4882a593Smuzhiyun break;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun printf(", %d carrier(s) %s", feature_carriers,
234*4882a593Smuzhiyun feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun printf(", %d video channel(s)\n", feature_video_channels);
237*4882a593Smuzhiyun }
238