1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2014
3*4882a593Smuzhiyun * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun /* Chrontel CH7301C DVI Transmitter */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <errno.h>
13*4882a593Smuzhiyun #include <i2c.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define CH7301_I2C_ADDR 0x75
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun enum {
18*4882a593Smuzhiyun CH7301_CM = 0x1c, /* Clock Mode Register */
19*4882a593Smuzhiyun CH7301_IC = 0x1d, /* Input Clock Register */
20*4882a593Smuzhiyun CH7301_GPIO = 0x1e, /* GPIO Control Register */
21*4882a593Smuzhiyun CH7301_IDF = 0x1f, /* Input Data Format Register */
22*4882a593Smuzhiyun CH7301_CD = 0x20, /* Connection Detect Register */
23*4882a593Smuzhiyun CH7301_DC = 0x21, /* DAC Control Register */
24*4882a593Smuzhiyun CH7301_HPD = 0x23, /* Hot Plug Detection Register */
25*4882a593Smuzhiyun CH7301_TCTL = 0x31, /* DVI Control Input Register */
26*4882a593Smuzhiyun CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
27*4882a593Smuzhiyun CH7301_TPD = 0x34, /* DVI PLL Divide Register */
28*4882a593Smuzhiyun CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
29*4882a593Smuzhiyun CH7301_TPF = 0x36, /* DVI PLL Filter Register */
30*4882a593Smuzhiyun CH7301_TCT = 0x37, /* DVI Clock Test Register */
31*4882a593Smuzhiyun CH7301_TSTP = 0x48, /* Test Pattern Register */
32*4882a593Smuzhiyun CH7301_PM = 0x49, /* Power Management register */
33*4882a593Smuzhiyun CH7301_VID = 0x4a, /* Version ID Register */
34*4882a593Smuzhiyun CH7301_DID = 0x4b, /* Device ID Register */
35*4882a593Smuzhiyun CH7301_DSP = 0x56, /* DVI Sync polarity Register */
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
39*4882a593Smuzhiyun
ch7301_probe(unsigned screen,bool power)40*4882a593Smuzhiyun int ch7301_probe(unsigned screen, bool power)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun u8 value;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun i2c_set_bus_num(ch7301_i2c[screen]);
45*4882a593Smuzhiyun if (i2c_probe(CH7301_I2C_ADDR))
46*4882a593Smuzhiyun return -1;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
49*4882a593Smuzhiyun if (value != 0x17)
50*4882a593Smuzhiyun return -1;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun if (power) {
53*4882a593Smuzhiyun i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
54*4882a593Smuzhiyun i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
55*4882a593Smuzhiyun i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
56*4882a593Smuzhiyun i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
57*4882a593Smuzhiyun i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
58*4882a593Smuzhiyun } else {
59*4882a593Smuzhiyun i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x00);
60*4882a593Smuzhiyun i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0x01);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return 0;
64*4882a593Smuzhiyun }
65