1*4882a593Smuzhiyun struct ihs_fpga { 2*4882a593Smuzhiyun u32 reflection_low; /* 0x0000 */ 3*4882a593Smuzhiyun u32 versions; /* 0x0004 */ 4*4882a593Smuzhiyun u32 fpga_version; /* 0x0008 */ 5*4882a593Smuzhiyun u32 fpga_features; /* 0x000c */ 6*4882a593Smuzhiyun u32 reserved0[4]; /* 0x0010 */ 7*4882a593Smuzhiyun u32 control; /* 0x0020 */ 8*4882a593Smuzhiyun u32 reserved1[375]; /* 0x0024 */ 9*4882a593Smuzhiyun u32 qsgmii_port_state[80]; /* 0x0600 */ 10*4882a593Smuzhiyun }; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun void print_hydra_version(uint index); 13*4882a593Smuzhiyun void hydra_initialize(void); 14*4882a593Smuzhiyun struct ihs_fpga *get_fpga(void); 15