1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013 Gateworks Corporation 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Author: Tim Harvey <tharvey@gateworks.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* i2c slave addresses */ 12*4882a593Smuzhiyun #define GSC_SC_ADDR 0x20 13*4882a593Smuzhiyun #define GSC_RTC_ADDR 0x68 14*4882a593Smuzhiyun #define GSC_HWMON_ADDR 0x29 15*4882a593Smuzhiyun #define GSC_EEPROM_ADDR 0x51 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* System Controller registers */ 18*4882a593Smuzhiyun enum { 19*4882a593Smuzhiyun GSC_SC_CTRL0 = 0x00, 20*4882a593Smuzhiyun GSC_SC_CTRL1 = 0x01, 21*4882a593Smuzhiyun GSC_SC_STATUS = 0x0a, 22*4882a593Smuzhiyun GSC_SC_FWCRC = 0x0c, 23*4882a593Smuzhiyun GSC_SC_FWVER = 0x0e, 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* System Controller Control1 bits */ 27*4882a593Smuzhiyun enum { 28*4882a593Smuzhiyun GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */ 29*4882a593Smuzhiyun GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */ 30*4882a593Smuzhiyun GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */ 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* System Controller Interrupt bits */ 34*4882a593Smuzhiyun enum { 35*4882a593Smuzhiyun GSC_SC_IRQ_PB = 0, /* Pushbutton switch */ 36*4882a593Smuzhiyun GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */ 37*4882a593Smuzhiyun GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */ 38*4882a593Smuzhiyun GSC_SC_IRQ_GPIO = 4, /* GPIO change */ 39*4882a593Smuzhiyun GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */ 40*4882a593Smuzhiyun GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */ 41*4882a593Smuzhiyun GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */ 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Hardware Monitor registers */ 45*4882a593Smuzhiyun enum { 46*4882a593Smuzhiyun GSC_HWMON_TEMP = 0x00, 47*4882a593Smuzhiyun GSC_HWMON_VIN = 0x02, 48*4882a593Smuzhiyun GSC_HWMON_VDD_3P3 = 0x05, 49*4882a593Smuzhiyun GSC_HWMON_VBATT = 0x08, 50*4882a593Smuzhiyun GSC_HWMON_VDD_5P0 = 0x0b, 51*4882a593Smuzhiyun GSC_HWMON_VDD_CORE = 0x0e, 52*4882a593Smuzhiyun GSC_HWMON_VDD_HIGH = 0x14, 53*4882a593Smuzhiyun GSC_HWMON_VDD_DDR = 0x17, 54*4882a593Smuzhiyun GSC_HWMON_VDD_SOC = 0x11, 55*4882a593Smuzhiyun GSC_HWMON_VDD_1P8 = 0x1d, 56*4882a593Smuzhiyun GSC_HWMON_VDD_IO2 = 0x20, 57*4882a593Smuzhiyun GSC_HWMON_VDD_2P5 = 0x23, 58*4882a593Smuzhiyun GSC_HWMON_VDD_IO3 = 0x26, 59*4882a593Smuzhiyun GSC_HWMON_VDD_IO4 = 0x29, 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * I2C transactions to the GSC are done via these functions which 64*4882a593Smuzhiyun * perform retries in the case of a busy GSC NAK'ing the transaction 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len); 67*4882a593Smuzhiyun int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len); 68*4882a593Smuzhiyun int gsc_info(int verbose); 69*4882a593Smuzhiyun int gsc_boot_wd_disable(void); 70*4882a593Smuzhiyun #endif 71*4882a593Smuzhiyun 72