1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DDR_H__ 8*4882a593Smuzhiyun #define __DDR_H__ 9*4882a593Smuzhiyun struct board_specific_parameters { 10*4882a593Smuzhiyun u32 n_ranks; 11*4882a593Smuzhiyun u32 datarate_mhz_high; 12*4882a593Smuzhiyun u32 rank_gb; 13*4882a593Smuzhiyun u32 clk_adjust; 14*4882a593Smuzhiyun u32 wrlvl_start; 15*4882a593Smuzhiyun u32 wrlvl_ctl_2; 16*4882a593Smuzhiyun u32 wrlvl_ctl_3; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * These tables contain all valid speeds we want to override with board 21*4882a593Smuzhiyun * specific parameters. datarate_mhz_high values need to be in ascending order 22*4882a593Smuzhiyun * for each n_ranks group. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun static const struct board_specific_parameters udimm0[] = { 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * memory controller 0 27*4882a593Smuzhiyun * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 28*4882a593Smuzhiyun * ranks| mhz| GB |adjst| start | ctl2 | ctl3 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a}, 31*4882a593Smuzhiyun {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09}, 32*4882a593Smuzhiyun {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b}, 33*4882a593Smuzhiyun {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a}, 34*4882a593Smuzhiyun {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, 35*4882a593Smuzhiyun {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, 36*4882a593Smuzhiyun {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a}, 37*4882a593Smuzhiyun {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a}, 38*4882a593Smuzhiyun {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a}, 39*4882a593Smuzhiyun {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b}, 40*4882a593Smuzhiyun {} 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun static const struct board_specific_parameters rdimm0[] = { 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * memory controller 0 46*4882a593Smuzhiyun * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 47*4882a593Smuzhiyun * ranks| mhz| GB |adjst| start | ctl2 | ctl3 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun {4, 1350, 0, 10, 9, 0x08070605, 0x06070806}, 50*4882a593Smuzhiyun {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906}, 51*4882a593Smuzhiyun {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, 52*4882a593Smuzhiyun {2, 1350, 0, 10, 9, 0x08070605, 0x06070806}, 53*4882a593Smuzhiyun {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, 54*4882a593Smuzhiyun {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, 55*4882a593Smuzhiyun {1, 1350, 0, 10, 9, 0x08070605, 0x06070806}, 56*4882a593Smuzhiyun {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, 57*4882a593Smuzhiyun {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07}, 58*4882a593Smuzhiyun {} 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * The three slots have slightly different timing. The center values are good 63*4882a593Smuzhiyun * for all slots. We use identical speed tables for them. In future use, if 64*4882a593Smuzhiyun * DIMMs require separated tables, make more entries as needed. 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun static const struct board_specific_parameters *udimms[] = { 67*4882a593Smuzhiyun udimm0, 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * The three slots have slightly different timing. See comments above. 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun static const struct board_specific_parameters *rdimms[] = { 74*4882a593Smuzhiyun rdimm0, 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #endif 79