1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <i2c.h>
9*4882a593Smuzhiyun #include <hwconfig.h>
10*4882a593Smuzhiyun #include <asm/mmu.h>
11*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
12*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h>
13*4882a593Smuzhiyun #include <asm/fsl_law.h>
14*4882a593Smuzhiyun #include "ddr.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)18*4882a593Smuzhiyun void fsl_ddr_board_options(memctl_options_t *popts,
19*4882a593Smuzhiyun dimm_params_t *pdimm,
20*4882a593Smuzhiyun unsigned int ctrl_num)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
23*4882a593Smuzhiyun ulong ddr_freq;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun if (ctrl_num > 2) {
26*4882a593Smuzhiyun printf("Not supported controller number %d\n", ctrl_num);
27*4882a593Smuzhiyun return;
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun if (!pdimm->n_ranks)
30*4882a593Smuzhiyun return;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * we use identical timing for all slots. If needed, change the code
34*4882a593Smuzhiyun * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun if (popts->registered_dimm_en)
37*4882a593Smuzhiyun pbsp = rdimms[0];
38*4882a593Smuzhiyun else
39*4882a593Smuzhiyun pbsp = udimms[0];
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
43*4882a593Smuzhiyun * freqency and n_banks specified in board_specific_parameters table.
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun ddr_freq = get_ddr_freq(0) / 1000000;
46*4882a593Smuzhiyun while (pbsp->datarate_mhz_high) {
47*4882a593Smuzhiyun if (pbsp->n_ranks == pdimm->n_ranks &&
48*4882a593Smuzhiyun (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
49*4882a593Smuzhiyun if (ddr_freq <= pbsp->datarate_mhz_high) {
50*4882a593Smuzhiyun popts->clk_adjust = pbsp->clk_adjust;
51*4882a593Smuzhiyun popts->wrlvl_start = pbsp->wrlvl_start;
52*4882a593Smuzhiyun popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
53*4882a593Smuzhiyun popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
54*4882a593Smuzhiyun goto found;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun pbsp_highest = pbsp;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun pbsp++;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun if (pbsp_highest) {
62*4882a593Smuzhiyun printf("Error: board specific timing not found for data\n"
63*4882a593Smuzhiyun "rate %lu MT/s\n"
64*4882a593Smuzhiyun "Trying to use the highest speed (%u) parameters\n",
65*4882a593Smuzhiyun ddr_freq, pbsp_highest->datarate_mhz_high);
66*4882a593Smuzhiyun popts->clk_adjust = pbsp_highest->clk_adjust;
67*4882a593Smuzhiyun popts->wrlvl_start = pbsp_highest->wrlvl_start;
68*4882a593Smuzhiyun popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
69*4882a593Smuzhiyun popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
70*4882a593Smuzhiyun } else {
71*4882a593Smuzhiyun panic("DIMM is not supported by this board");
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun found:
74*4882a593Smuzhiyun debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
75*4882a593Smuzhiyun "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"
76*4882a593Smuzhiyun "wrlvl_ctrl_3 0x%x\n",
77*4882a593Smuzhiyun pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
78*4882a593Smuzhiyun pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
79*4882a593Smuzhiyun pbsp->wrlvl_ctl_3);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /*
82*4882a593Smuzhiyun * Factors to consider for half-strength driver enable:
83*4882a593Smuzhiyun * - number of DIMMs installed
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun popts->half_strength_driver_enable = 0;
86*4882a593Smuzhiyun /*
87*4882a593Smuzhiyun * Write leveling override
88*4882a593Smuzhiyun */
89*4882a593Smuzhiyun popts->wrlvl_override = 1;
90*4882a593Smuzhiyun popts->wrlvl_sample = 0xf;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /*
93*4882a593Smuzhiyun * Rtt and Rtt_WR override
94*4882a593Smuzhiyun */
95*4882a593Smuzhiyun popts->rtt_override = 0;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* Enable ZQ calibration */
98*4882a593Smuzhiyun popts->zq_en = 1;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* DHC_EN =1, ODT = 75 Ohm */
101*4882a593Smuzhiyun popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
102*4882a593Smuzhiyun popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* optimize cpo for erratum A-009942 */
105*4882a593Smuzhiyun popts->cpo_sample = 0x64;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
dram_init(void)108*4882a593Smuzhiyun int dram_init(void)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun phys_size_t dram_size;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun puts("Initializing....using SPD\n");
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
115*4882a593Smuzhiyun dram_size = fsl_ddr_sdram();
116*4882a593Smuzhiyun #else
117*4882a593Smuzhiyun /* DDR has been initialised by first stage boot loader */
118*4882a593Smuzhiyun dram_size = fsl_ddr_sdram_size();
119*4882a593Smuzhiyun #endif
120*4882a593Smuzhiyun dram_size = setup_ddr_tlbs(dram_size / 0x100000);
121*4882a593Smuzhiyun dram_size *= 0x100000;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun gd->ram_size = dram_size;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun return 0;
126*4882a593Smuzhiyun }
127