1*4882a593Smuzhiyun /** 2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Author: Chunhe Lan <Chunhe.Lan@freescale.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This file provides support for the ngPIXIS, a board-specific FPGA used on 9*4882a593Smuzhiyun * some Freescale reference boards. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * CPLD register set. Feel free to add board-specific #ifdefs where necessary. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun struct cpld_data { 16*4882a593Smuzhiyun u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */ 17*4882a593Smuzhiyun u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */ 18*4882a593Smuzhiyun u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */ 19*4882a593Smuzhiyun u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */ 20*4882a593Smuzhiyun u8 hw_ver; /* 0x04 - PCBA Version Register */ 21*4882a593Smuzhiyun u8 software_on; /* 0x05 - Override Physical Switch Enable Register */ 22*4882a593Smuzhiyun u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */ 23*4882a593Smuzhiyun u8 res0; /* 0x07 - not used */ 24*4882a593Smuzhiyun u8 vbank; /* 0x08 - Flash Bank Selection Control Register */ 25*4882a593Smuzhiyun u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */ 26*4882a593Smuzhiyun u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */ 27*4882a593Smuzhiyun u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */ 28*4882a593Smuzhiyun u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */ 29*4882a593Smuzhiyun u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/ 30*4882a593Smuzhiyun u8 global_reset;/* 0x0e - Reset System With Default Registers Value */ 31*4882a593Smuzhiyun u8 res1; /* 0x0f - not used */ 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define CPLD_BANK_SEL_MASK 0x07 35*4882a593Smuzhiyun #define CPLD_BANK_SEL_EN 0x04 36*4882a593Smuzhiyun #define CPLD_SYSTEM_RESET 0x01 37*4882a593Smuzhiyun #define CPLD_SELECT_BANK0 0x00 38*4882a593Smuzhiyun #define CPLD_SELECT_BANK4 0x04 39*4882a593Smuzhiyun #define CPLD_DEFAULT_BANK 0x01 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Pointer to the CPLD register set */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun u8 cpld_read(unsigned int reg); 44*4882a593Smuzhiyun void cpld_write(unsigned int reg, u8 value); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) 47*4882a593Smuzhiyun #define CPLD_WRITE(reg, value) \ 48*4882a593Smuzhiyun cpld_write(offsetof(struct cpld_data, reg), value) 49*4882a593Smuzhiyun 50