1*4882a593Smuzhiyun /**
2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This file provides support for the board-specific CPLD used on some Freescale
9*4882a593Smuzhiyun * reference boards.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The following macros need to be defined:
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
14*4882a593Smuzhiyun * CPLD register map
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <common.h>
19*4882a593Smuzhiyun #include <command.h>
20*4882a593Smuzhiyun #include <asm/io.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include "cpld.h"
23*4882a593Smuzhiyun
cpld_read(unsigned int reg)24*4882a593Smuzhiyun u8 cpld_read(unsigned int reg)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun void *p = (void *)CONFIG_SYS_CPLD_BASE;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun return in_8(p + reg);
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
cpld_write(unsigned int reg,u8 value)31*4882a593Smuzhiyun void cpld_write(unsigned int reg, u8 value)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun void *p = (void *)CONFIG_SYS_CPLD_BASE;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun out_8(p + reg, value);
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /**
39*4882a593Smuzhiyun * Set the boot bank to the alternate bank
40*4882a593Smuzhiyun */
cpld_set_altbank(void)41*4882a593Smuzhiyun void cpld_set_altbank(void)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun u8 val, curbank, altbank, override;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun val = CPLD_READ(vbank);
46*4882a593Smuzhiyun curbank = val & CPLD_BANK_SEL_MASK;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun switch (curbank) {
49*4882a593Smuzhiyun case CPLD_SELECT_BANK0:
50*4882a593Smuzhiyun case CPLD_SELECT_BANK4:
51*4882a593Smuzhiyun altbank = CPLD_SELECT_BANK4;
52*4882a593Smuzhiyun CPLD_WRITE(vbank, altbank);
53*4882a593Smuzhiyun override = CPLD_READ(software_on);
54*4882a593Smuzhiyun CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
55*4882a593Smuzhiyun CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
56*4882a593Smuzhiyun break;
57*4882a593Smuzhiyun default:
58*4882a593Smuzhiyun printf("CPLD Altbank Fail: Invalid value!\n");
59*4882a593Smuzhiyun return;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /**
64*4882a593Smuzhiyun * Set the boot bank to the default bank
65*4882a593Smuzhiyun */
cpld_set_defbank(void)66*4882a593Smuzhiyun void cpld_set_defbank(void)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun u8 val;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun val = CPLD_DEFAULT_BANK;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun CPLD_WRITE(global_reset, val);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #ifdef DEBUG
cpld_dump_regs(void)76*4882a593Smuzhiyun static void cpld_dump_regs(void)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1));
79*4882a593Smuzhiyun printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2));
80*4882a593Smuzhiyun printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver));
81*4882a593Smuzhiyun printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver));
82*4882a593Smuzhiyun printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
83*4882a593Smuzhiyun printf("software_on = 0x%02x\n", CPLD_READ(software_on));
84*4882a593Smuzhiyun printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src));
85*4882a593Smuzhiyun printf("res0 = 0x%02x\n", CPLD_READ(res0));
86*4882a593Smuzhiyun printf("vbank = 0x%02x\n", CPLD_READ(vbank));
87*4882a593Smuzhiyun printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk));
88*4882a593Smuzhiyun printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status));
89*4882a593Smuzhiyun printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status));
90*4882a593Smuzhiyun printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status));
91*4882a593Smuzhiyun printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset));
92*4882a593Smuzhiyun printf("global_reset = 0x%02x\n", CPLD_READ(global_reset));
93*4882a593Smuzhiyun printf("res1 = 0x%02x\n", CPLD_READ(res1));
94*4882a593Smuzhiyun putc('\n');
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun #endif
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD
do_cpld(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])99*4882a593Smuzhiyun int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun int rc = 0;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (argc <= 1)
104*4882a593Smuzhiyun return cmd_usage(cmdtp);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun if (strcmp(argv[1], "reset") == 0) {
107*4882a593Smuzhiyun if (strcmp(argv[2], "altbank") == 0)
108*4882a593Smuzhiyun cpld_set_altbank();
109*4882a593Smuzhiyun else
110*4882a593Smuzhiyun cpld_set_defbank();
111*4882a593Smuzhiyun #ifdef DEBUG
112*4882a593Smuzhiyun } else if (strcmp(argv[1], "dump") == 0) {
113*4882a593Smuzhiyun cpld_dump_regs();
114*4882a593Smuzhiyun #endif
115*4882a593Smuzhiyun } else
116*4882a593Smuzhiyun rc = cmd_usage(cmdtp);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun return rc;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun U_BOOT_CMD(
122*4882a593Smuzhiyun cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
123*4882a593Smuzhiyun "Reset the board or alternate bank",
124*4882a593Smuzhiyun "reset - reset to default bank\n"
125*4882a593Smuzhiyun "cpld reset altbank - reset to alternate bank\n"
126*4882a593Smuzhiyun #ifdef DEBUG
127*4882a593Smuzhiyun "cpld dump - display the CPLD registers\n"
128*4882a593Smuzhiyun #endif
129*4882a593Smuzhiyun );
130*4882a593Smuzhiyun #endif
131