1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __T4020QDS_QIXIS_H__ 8*4882a593Smuzhiyun #define __T4020QDS_QIXIS_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Definitions of QIXIS Registers for T4020QDS */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ 13*4882a593Smuzhiyun #define BRDCFG4_EMISEL_MASK 0xE0 14*4882a593Smuzhiyun #define BRDCFG4_EMISEL_SHIFT 5 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* SYSCLK */ 17*4882a593Smuzhiyun #define QIXIS_SYSCLK_66 0x0 18*4882a593Smuzhiyun #define QIXIS_SYSCLK_83 0x1 19*4882a593Smuzhiyun #define QIXIS_SYSCLK_100 0x2 20*4882a593Smuzhiyun #define QIXIS_SYSCLK_125 0x3 21*4882a593Smuzhiyun #define QIXIS_SYSCLK_133 0x4 22*4882a593Smuzhiyun #define QIXIS_SYSCLK_150 0x5 23*4882a593Smuzhiyun #define QIXIS_SYSCLK_160 0x6 24*4882a593Smuzhiyun #define QIXIS_SYSCLK_166 0x7 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* DDRCLK */ 27*4882a593Smuzhiyun #define QIXIS_DDRCLK_66 0x0 28*4882a593Smuzhiyun #define QIXIS_DDRCLK_100 0x1 29*4882a593Smuzhiyun #define QIXIS_DDRCLK_125 0x2 30*4882a593Smuzhiyun #define QIXIS_DDRCLK_133 0x3 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define BRDCFG12_SD3EN_MASK 0x20 35*4882a593Smuzhiyun #define BRDCFG12_SD3MX_MASK 0x08 36*4882a593Smuzhiyun #define BRDCFG12_SD3MX_SLOT5 0x08 37*4882a593Smuzhiyun #define BRDCFG12_SD3MX_SLOT6 0x00 38*4882a593Smuzhiyun #define BRDCFG12_SD4EN_MASK 0x04 39*4882a593Smuzhiyun #define BRDCFG12_SD4MX_MASK 0x03 40*4882a593Smuzhiyun #define BRDCFG12_SD4MX_SLOT7 0x02 41*4882a593Smuzhiyun #define BRDCFG12_SD4MX_SLOT8 0x01 42*4882a593Smuzhiyun #define BRDCFG12_SD4MX_AURO_SATA 0x00 43*4882a593Smuzhiyun #endif 44