1*4882a593Smuzhiyun /* Copyright 2014 Freescale Semiconductor, Inc.
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <console.h>
8*4882a593Smuzhiyun #include <environment.h>
9*4882a593Smuzhiyun #include <asm/spl.h>
10*4882a593Smuzhiyun #include <malloc.h>
11*4882a593Smuzhiyun #include <ns16550.h>
12*4882a593Smuzhiyun #include <nand.h>
13*4882a593Smuzhiyun #include <mmc.h>
14*4882a593Smuzhiyun #include <fsl_esdhc.h>
15*4882a593Smuzhiyun #include <i2c.h>
16*4882a593Smuzhiyun #include "../common/qixis.h"
17*4882a593Smuzhiyun #include "t4240qds_qixis.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
22*4882a593Smuzhiyun
get_effective_memsize(void)23*4882a593Smuzhiyun phys_size_t get_effective_memsize(void)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun return CONFIG_SYS_L3_SIZE;
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
get_board_sys_clk(void)28*4882a593Smuzhiyun unsigned long get_board_sys_clk(void)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun switch (sysclk_conf & 0x0F) {
33*4882a593Smuzhiyun case QIXIS_SYSCLK_83:
34*4882a593Smuzhiyun return 83333333;
35*4882a593Smuzhiyun case QIXIS_SYSCLK_100:
36*4882a593Smuzhiyun return 100000000;
37*4882a593Smuzhiyun case QIXIS_SYSCLK_125:
38*4882a593Smuzhiyun return 125000000;
39*4882a593Smuzhiyun case QIXIS_SYSCLK_133:
40*4882a593Smuzhiyun return 133333333;
41*4882a593Smuzhiyun case QIXIS_SYSCLK_150:
42*4882a593Smuzhiyun return 150000000;
43*4882a593Smuzhiyun case QIXIS_SYSCLK_160:
44*4882a593Smuzhiyun return 160000000;
45*4882a593Smuzhiyun case QIXIS_SYSCLK_166:
46*4882a593Smuzhiyun return 166666666;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun return 66666666;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
get_board_ddr_clk(void)51*4882a593Smuzhiyun unsigned long get_board_ddr_clk(void)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun switch ((ddrclk_conf & 0x30) >> 4) {
56*4882a593Smuzhiyun case QIXIS_DDRCLK_100:
57*4882a593Smuzhiyun return 100000000;
58*4882a593Smuzhiyun case QIXIS_DDRCLK_125:
59*4882a593Smuzhiyun return 125000000;
60*4882a593Smuzhiyun case QIXIS_DDRCLK_133:
61*4882a593Smuzhiyun return 133333333;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun return 66666666;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
board_init_f(ulong bootflag)66*4882a593Smuzhiyun void board_init_f(ulong bootflag)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun u32 plat_ratio, sys_clk, ccb_clk;
69*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
70*4882a593Smuzhiyun #ifdef CONFIG_SPL_NAND_BOOT
71*4882a593Smuzhiyun u32 porsr1, pinctl;
72*4882a593Smuzhiyun #endif
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #ifdef CONFIG_SPL_NAND_BOOT
75*4882a593Smuzhiyun porsr1 = in_be32(&gur->porsr1);
76*4882a593Smuzhiyun pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
77*4882a593Smuzhiyun out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
78*4882a593Smuzhiyun #endif
79*4882a593Smuzhiyun /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
80*4882a593Smuzhiyun memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Update GD pointer */
83*4882a593Smuzhiyun gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* compiler optimization barrier needed for GCC >= 3.4 */
86*4882a593Smuzhiyun __asm__ __volatile__("" : : : "memory");
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun console_init_f();
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* initialize selected port with appropriate baud rate */
91*4882a593Smuzhiyun sys_clk = get_board_sys_clk();
92*4882a593Smuzhiyun plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
93*4882a593Smuzhiyun ccb_clk = sys_clk * plat_ratio / 2;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
96*4882a593Smuzhiyun ccb_clk / 16 / CONFIG_BAUDRATE);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #ifdef CONFIG_SPL_MMC_BOOT
99*4882a593Smuzhiyun puts("\nSD boot...\n");
100*4882a593Smuzhiyun #elif defined(CONFIG_SPL_NAND_BOOT)
101*4882a593Smuzhiyun puts("\nNAND boot...\n");
102*4882a593Smuzhiyun #endif
103*4882a593Smuzhiyun relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
board_init_r(gd_t * gd,ulong dest_addr)106*4882a593Smuzhiyun void board_init_r(gd_t *gd, ulong dest_addr)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun bd_t *bd;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun bd = (bd_t *)(gd + sizeof(gd_t));
111*4882a593Smuzhiyun memset(bd, 0, sizeof(bd_t));
112*4882a593Smuzhiyun gd->bd = bd;
113*4882a593Smuzhiyun bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
114*4882a593Smuzhiyun bd->bi_memsize = CONFIG_SYS_L3_SIZE;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun arch_cpu_init();
117*4882a593Smuzhiyun get_clocks();
118*4882a593Smuzhiyun mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
119*4882a593Smuzhiyun CONFIG_SPL_RELOC_MALLOC_SIZE);
120*4882a593Smuzhiyun gd->flags |= GD_FLG_FULL_MALLOC_INIT;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun #ifdef CONFIG_SPL_NAND_BOOT
123*4882a593Smuzhiyun nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
124*4882a593Smuzhiyun (uchar *)CONFIG_ENV_ADDR);
125*4882a593Smuzhiyun #endif
126*4882a593Smuzhiyun #ifdef CONFIG_SPL_MMC_BOOT
127*4882a593Smuzhiyun mmc_initialize(bd);
128*4882a593Smuzhiyun mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
129*4882a593Smuzhiyun (uchar *)CONFIG_ENV_ADDR);
130*4882a593Smuzhiyun #endif
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
133*4882a593Smuzhiyun gd->env_valid = ENV_VALID;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun i2c_init_all();
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun dram_init();
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #ifdef CONFIG_SPL_MMC_BOOT
140*4882a593Smuzhiyun mmc_boot();
141*4882a593Smuzhiyun #elif defined(CONFIG_SPL_NAND_BOOT)
142*4882a593Smuzhiyun nand_boot();
143*4882a593Smuzhiyun #endif
144*4882a593Smuzhiyun }
145