1 /* Copyright 2014 Freescale Semiconductor, Inc.
2 *
3 * SPDX-License-Identifier: GPL-2.0+
4 */
5
6 #include <common.h>
7 #include <console.h>
8 #include <environment.h>
9 #include <asm/spl.h>
10 #include <malloc.h>
11 #include <ns16550.h>
12 #include <nand.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <i2c.h>
16 #include "../common/qixis.h"
17 #include "t4240qds_qixis.h"
18
19 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
20
21 DECLARE_GLOBAL_DATA_PTR;
22
get_effective_memsize(void)23 phys_size_t get_effective_memsize(void)
24 {
25 return CONFIG_SYS_L3_SIZE;
26 }
27
get_board_sys_clk(void)28 unsigned long get_board_sys_clk(void)
29 {
30 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
31
32 switch (sysclk_conf & 0x0F) {
33 case QIXIS_SYSCLK_83:
34 return 83333333;
35 case QIXIS_SYSCLK_100:
36 return 100000000;
37 case QIXIS_SYSCLK_125:
38 return 125000000;
39 case QIXIS_SYSCLK_133:
40 return 133333333;
41 case QIXIS_SYSCLK_150:
42 return 150000000;
43 case QIXIS_SYSCLK_160:
44 return 160000000;
45 case QIXIS_SYSCLK_166:
46 return 166666666;
47 }
48 return 66666666;
49 }
50
get_board_ddr_clk(void)51 unsigned long get_board_ddr_clk(void)
52 {
53 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
54
55 switch ((ddrclk_conf & 0x30) >> 4) {
56 case QIXIS_DDRCLK_100:
57 return 100000000;
58 case QIXIS_DDRCLK_125:
59 return 125000000;
60 case QIXIS_DDRCLK_133:
61 return 133333333;
62 }
63 return 66666666;
64 }
65
board_init_f(ulong bootflag)66 void board_init_f(ulong bootflag)
67 {
68 u32 plat_ratio, sys_clk, ccb_clk;
69 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
70 #ifdef CONFIG_SPL_NAND_BOOT
71 u32 porsr1, pinctl;
72 #endif
73
74 #ifdef CONFIG_SPL_NAND_BOOT
75 porsr1 = in_be32(&gur->porsr1);
76 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
77 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
78 #endif
79 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
80 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
81
82 /* Update GD pointer */
83 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
84
85 /* compiler optimization barrier needed for GCC >= 3.4 */
86 __asm__ __volatile__("" : : : "memory");
87
88 console_init_f();
89
90 /* initialize selected port with appropriate baud rate */
91 sys_clk = get_board_sys_clk();
92 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
93 ccb_clk = sys_clk * plat_ratio / 2;
94
95 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
96 ccb_clk / 16 / CONFIG_BAUDRATE);
97
98 #ifdef CONFIG_SPL_MMC_BOOT
99 puts("\nSD boot...\n");
100 #elif defined(CONFIG_SPL_NAND_BOOT)
101 puts("\nNAND boot...\n");
102 #endif
103 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
104 }
105
board_init_r(gd_t * gd,ulong dest_addr)106 void board_init_r(gd_t *gd, ulong dest_addr)
107 {
108 bd_t *bd;
109
110 bd = (bd_t *)(gd + sizeof(gd_t));
111 memset(bd, 0, sizeof(bd_t));
112 gd->bd = bd;
113 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
114 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
115
116 arch_cpu_init();
117 get_clocks();
118 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
119 CONFIG_SPL_RELOC_MALLOC_SIZE);
120 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
121
122 #ifdef CONFIG_SPL_NAND_BOOT
123 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
124 (uchar *)CONFIG_ENV_ADDR);
125 #endif
126 #ifdef CONFIG_SPL_MMC_BOOT
127 mmc_initialize(bd);
128 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
129 (uchar *)CONFIG_ENV_ADDR);
130 #endif
131
132 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
133 gd->env_valid = ENV_VALID;
134
135 i2c_init_all();
136
137 dram_init();
138
139 #ifdef CONFIG_SPL_MMC_BOOT
140 mmc_boot();
141 #elif defined(CONFIG_SPL_NAND_BOOT)
142 nand_boot();
143 #endif
144 }
145