1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2009-2013 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <command.h>
9*4882a593Smuzhiyun #include <i2c.h>
10*4882a593Smuzhiyun #include <netdev.h>
11*4882a593Smuzhiyun #include <linux/compiler.h>
12*4882a593Smuzhiyun #include <asm/mmu.h>
13*4882a593Smuzhiyun #include <asm/processor.h>
14*4882a593Smuzhiyun #include <asm/immap_85xx.h>
15*4882a593Smuzhiyun #include <asm/fsl_law.h>
16*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
17*4882a593Smuzhiyun #include <asm/fsl_liodn.h>
18*4882a593Smuzhiyun #include <fm_eth.h>
19*4882a593Smuzhiyun #include "t208xrdb.h"
20*4882a593Smuzhiyun #include "cpld.h"
21*4882a593Smuzhiyun #include "../common/vid.h"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
24*4882a593Smuzhiyun
checkboard(void)25*4882a593Smuzhiyun int checkboard(void)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun struct cpu_type *cpu = gd->arch.cpu;
28*4882a593Smuzhiyun static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun printf("Board: %sRDB, ", cpu->name);
31*4882a593Smuzhiyun printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
32*4882a593Smuzhiyun CPLD_READ(hw_ver), CPLD_READ(sw_ver));
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #ifdef CONFIG_SDCARD
35*4882a593Smuzhiyun puts("SD/MMC\n");
36*4882a593Smuzhiyun #elif CONFIG_SPIFLASH
37*4882a593Smuzhiyun puts("SPI\n");
38*4882a593Smuzhiyun #else
39*4882a593Smuzhiyun u8 reg;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun reg = CPLD_READ(flash_csr);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun if (reg & CPLD_BOOT_SEL) {
44*4882a593Smuzhiyun puts("NAND\n");
45*4882a593Smuzhiyun } else {
46*4882a593Smuzhiyun reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
47*4882a593Smuzhiyun printf("NOR vBank%d\n", reg);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun #endif
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun puts("SERDES Reference Clocks:\n");
52*4882a593Smuzhiyun printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
53*4882a593Smuzhiyun printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun return 0;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
board_early_init_r(void)58*4882a593Smuzhiyun int board_early_init_r(void)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
61*4882a593Smuzhiyun int flash_esel = find_tlb_idx((void *)flashbase, 1);
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun * Remap Boot flash + PROMJET region to caching-inhibited
64*4882a593Smuzhiyun * so that flash can be erased properly.
65*4882a593Smuzhiyun */
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* Flush d-cache and invalidate i-cache of any FLASH data */
68*4882a593Smuzhiyun flush_dcache();
69*4882a593Smuzhiyun invalidate_icache();
70*4882a593Smuzhiyun if (flash_esel == -1) {
71*4882a593Smuzhiyun /* very unlikely unless something is messed up */
72*4882a593Smuzhiyun puts("Error: Could not find TLB for FLASH BASE\n");
73*4882a593Smuzhiyun flash_esel = 2; /* give our best effort to continue */
74*4882a593Smuzhiyun } else {
75*4882a593Smuzhiyun /* invalidate existing TLB entry for flash + promjet */
76*4882a593Smuzhiyun disable_tlb(flash_esel);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
80*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
81*4882a593Smuzhiyun 0, flash_esel, BOOKE_PAGESZ_256M, 1);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /*
84*4882a593Smuzhiyun * Adjust core voltage according to voltage ID
85*4882a593Smuzhiyun * This function changes I2C mux to channel 2.
86*4882a593Smuzhiyun */
87*4882a593Smuzhiyun if (adjust_vdd(0))
88*4882a593Smuzhiyun printf("Warning: Adjusting core voltage failed.\n");
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
get_board_sys_clk(void)92*4882a593Smuzhiyun unsigned long get_board_sys_clk(void)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun return CONFIG_SYS_CLK_FREQ;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
get_board_ddr_clk(void)97*4882a593Smuzhiyun unsigned long get_board_ddr_clk(void)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun return CONFIG_DDR_CLK_FREQ;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
misc_init_r(void)102*4882a593Smuzhiyun int misc_init_r(void)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun u8 reg;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* Reset CS4315 PHY */
107*4882a593Smuzhiyun reg = CPLD_READ(reset_ctl);
108*4882a593Smuzhiyun reg |= CPLD_RSTCON_EDC_RST;
109*4882a593Smuzhiyun CPLD_WRITE(reset_ctl, reg);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun return 0;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
ft_board_setup(void * blob,bd_t * bd)114*4882a593Smuzhiyun int ft_board_setup(void *blob, bd_t *bd)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun phys_addr_t base;
117*4882a593Smuzhiyun phys_size_t size;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun ft_cpu_setup(blob, bd);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun base = env_get_bootm_low();
122*4882a593Smuzhiyun size = env_get_bootm_size();
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun fdt_fixup_memory(blob, (u64)base, (u64)size);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #ifdef CONFIG_PCI
127*4882a593Smuzhiyun pci_of_setup(blob, bd);
128*4882a593Smuzhiyun #endif
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun fdt_fixup_liodn(blob);
131*4882a593Smuzhiyun fsl_fdt_fixup_dr_usb(blob, bd);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun #ifdef CONFIG_SYS_DPAA_FMAN
134*4882a593Smuzhiyun fdt_fixup_fman_ethernet(blob);
135*4882a593Smuzhiyun fdt_fixup_board_enet(blob);
136*4882a593Smuzhiyun #endif
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun return 0;
139*4882a593Smuzhiyun }
140