1*4882a593Smuzhiyun# 2*4882a593Smuzhiyun# Copyright 2013 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun# 4*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun# 6*4882a593Smuzhiyun# Refer doc/README.pblimage for more details about how-to configure 7*4882a593Smuzhiyun# and create PBL boot image 8*4882a593Smuzhiyun# 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#PBI commands 11*4882a593Smuzhiyun#Initialize CPC1 12*4882a593Smuzhiyun09010000 00200400 13*4882a593Smuzhiyun09138000 00000000 14*4882a593Smuzhiyun091380c0 00000100 15*4882a593Smuzhiyun#512KB SRAM 16*4882a593Smuzhiyun09010100 00000000 17*4882a593Smuzhiyun09010104 fff80009 18*4882a593Smuzhiyun09010f00 08000000 19*4882a593Smuzhiyun#enable CPC1 20*4882a593Smuzhiyun09010000 80000000 21*4882a593Smuzhiyun#Configure LAW for CPC1 22*4882a593Smuzhiyun09000d00 00000000 23*4882a593Smuzhiyun09000d04 fff80000 24*4882a593Smuzhiyun09000d08 81000012 25*4882a593Smuzhiyun#Initialize eSPI controller, default configuration is slow for eSPI to 26*4882a593Smuzhiyun#load data, this configuration comes from u-boot eSPI driver. 27*4882a593Smuzhiyun09110000 80000403 28*4882a593Smuzhiyun09110020 2d170008 29*4882a593Smuzhiyun09110024 00100008 30*4882a593Smuzhiyun09110028 00100008 31*4882a593Smuzhiyun0911002c 00100008 32*4882a593Smuzhiyun#Errata for slowing down the MDC clock to make it <= 2.5 MHZ 33*4882a593Smuzhiyun094fc030 00008148 34*4882a593Smuzhiyun094fd030 00008148 35*4882a593Smuzhiyun#Configure alternate space 36*4882a593Smuzhiyun09000010 00000000 37*4882a593Smuzhiyun09000014 ff000000 38*4882a593Smuzhiyun09000018 81000000 39*4882a593Smuzhiyun#Flush PBL data 40*4882a593Smuzhiyun091380c0 00100000 41