1*4882a593Smuzhiyun /* Copyright 2013 Freescale Semiconductor, Inc.
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <console.h>
8*4882a593Smuzhiyun #include <environment.h>
9*4882a593Smuzhiyun #include <malloc.h>
10*4882a593Smuzhiyun #include <ns16550.h>
11*4882a593Smuzhiyun #include <nand.h>
12*4882a593Smuzhiyun #include <i2c.h>
13*4882a593Smuzhiyun #include <mmc.h>
14*4882a593Smuzhiyun #include <fsl_esdhc.h>
15*4882a593Smuzhiyun #include <spi_flash.h>
16*4882a593Smuzhiyun #include "../common/spl.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
19*4882a593Smuzhiyun
get_effective_memsize(void)20*4882a593Smuzhiyun phys_size_t get_effective_memsize(void)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun return CONFIG_SYS_L3_SIZE;
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
get_board_sys_clk(void)25*4882a593Smuzhiyun unsigned long get_board_sys_clk(void)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun return CONFIG_SYS_CLK_FREQ;
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
get_board_ddr_clk(void)30*4882a593Smuzhiyun unsigned long get_board_ddr_clk(void)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun return CONFIG_DDR_CLK_FREQ;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
board_init_f(ulong bootflag)35*4882a593Smuzhiyun void board_init_f(ulong bootflag)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun u32 plat_ratio, sys_clk, ccb_clk;
38*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
41*4882a593Smuzhiyun memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* Update GD pointer */
44*4882a593Smuzhiyun gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun console_init_f();
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* initialize selected port with appropriate baud rate */
49*4882a593Smuzhiyun sys_clk = get_board_sys_clk();
50*4882a593Smuzhiyun plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
51*4882a593Smuzhiyun ccb_clk = sys_clk * plat_ratio / 2;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
54*4882a593Smuzhiyun ccb_clk / 16 / CONFIG_BAUDRATE);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #if defined(CONFIG_SPL_MMC_BOOT)
57*4882a593Smuzhiyun puts("\nSD boot...\n");
58*4882a593Smuzhiyun #elif defined(CONFIG_SPL_SPI_BOOT)
59*4882a593Smuzhiyun puts("\nSPI boot...\n");
60*4882a593Smuzhiyun #elif defined(CONFIG_SPL_NAND_BOOT)
61*4882a593Smuzhiyun puts("\nNAND boot...\n");
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
board_init_r(gd_t * gd,ulong dest_addr)67*4882a593Smuzhiyun void board_init_r(gd_t *gd, ulong dest_addr)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun bd_t *bd;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun bd = (bd_t *)(gd + sizeof(gd_t));
72*4882a593Smuzhiyun memset(bd, 0, sizeof(bd_t));
73*4882a593Smuzhiyun gd->bd = bd;
74*4882a593Smuzhiyun bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
75*4882a593Smuzhiyun bd->bi_memsize = CONFIG_SYS_L3_SIZE;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun arch_cpu_init();
78*4882a593Smuzhiyun get_clocks();
79*4882a593Smuzhiyun mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
80*4882a593Smuzhiyun CONFIG_SPL_RELOC_MALLOC_SIZE);
81*4882a593Smuzhiyun gd->flags |= GD_FLG_FULL_MALLOC_INIT;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #ifdef CONFIG_SPL_NAND_BOOT
84*4882a593Smuzhiyun nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
85*4882a593Smuzhiyun (uchar *)CONFIG_ENV_ADDR);
86*4882a593Smuzhiyun #endif
87*4882a593Smuzhiyun #ifdef CONFIG_SPL_MMC_BOOT
88*4882a593Smuzhiyun mmc_initialize(bd);
89*4882a593Smuzhiyun mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
90*4882a593Smuzhiyun (uchar *)CONFIG_ENV_ADDR);
91*4882a593Smuzhiyun #endif
92*4882a593Smuzhiyun #ifdef CONFIG_SPL_SPI_BOOT
93*4882a593Smuzhiyun fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
94*4882a593Smuzhiyun (uchar *)CONFIG_ENV_ADDR);
95*4882a593Smuzhiyun #endif
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
98*4882a593Smuzhiyun gd->env_valid = ENV_VALID;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun i2c_init_all();
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun dram_init();
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun #ifdef CONFIG_SPL_MMC_BOOT
105*4882a593Smuzhiyun mmc_boot();
106*4882a593Smuzhiyun #elif defined(CONFIG_SPL_SPI_BOOT)
107*4882a593Smuzhiyun fsl_spi_boot();
108*4882a593Smuzhiyun #elif defined(CONFIG_SPL_NAND_BOOT)
109*4882a593Smuzhiyun nand_boot();
110*4882a593Smuzhiyun #endif
111*4882a593Smuzhiyun }
112