1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008-2014 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2000 5*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <asm/fsl_law.h> 12*4882a593Smuzhiyun #include <asm/mmu.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct law_entry law_table[] = { 15*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), 16*4882a593Smuzhiyun #ifdef CONFIG_SYS_BMAN_MEM_PHYS 17*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), 18*4882a593Smuzhiyun #endif 19*4882a593Smuzhiyun #ifdef CONFIG_SYS_QMAN_MEM_PHYS 20*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), 21*4882a593Smuzhiyun #endif 22*4882a593Smuzhiyun #ifdef CONFIG_SYS_CPLD_BASE_PHYS 23*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), 24*4882a593Smuzhiyun #endif 25*4882a593Smuzhiyun #ifdef CONFIG_SYS_DCSRBAR_PHYS 26*4882a593Smuzhiyun /* Limit DCSR to 32M to access NPC Trace Buffer */ 27*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), 28*4882a593Smuzhiyun #endif 29*4882a593Smuzhiyun #ifdef CONFIG_SYS_NAND_BASE_PHYS 30*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun int num_law_entries = ARRAY_SIZE(law_table); 35