1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Shengzhou Liu <Shengzhou.Liu@freescale.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <command.h>
11*4882a593Smuzhiyun #include <netdev.h>
12*4882a593Smuzhiyun #include <asm/mmu.h>
13*4882a593Smuzhiyun #include <asm/processor.h>
14*4882a593Smuzhiyun #include <asm/immap_85xx.h>
15*4882a593Smuzhiyun #include <asm/fsl_law.h>
16*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
17*4882a593Smuzhiyun #include <asm/fsl_portals.h>
18*4882a593Smuzhiyun #include <asm/fsl_liodn.h>
19*4882a593Smuzhiyun #include <malloc.h>
20*4882a593Smuzhiyun #include <fm_eth.h>
21*4882a593Smuzhiyun #include <fsl_mdio.h>
22*4882a593Smuzhiyun #include <miiphy.h>
23*4882a593Smuzhiyun #include <phy.h>
24*4882a593Smuzhiyun #include <fsl_dtsec.h>
25*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
26*4882a593Smuzhiyun
board_eth_init(bd_t * bis)27*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun #if defined(CONFIG_FMAN_ENET)
30*4882a593Smuzhiyun int i, interface;
31*4882a593Smuzhiyun struct memac_mdio_info dtsec_mdio_info;
32*4882a593Smuzhiyun struct memac_mdio_info tgec_mdio_info;
33*4882a593Smuzhiyun struct mii_dev *dev;
34*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
35*4882a593Smuzhiyun u32 srds_s1;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun srds_s1 = in_be32(&gur->rcwsr[4]) &
38*4882a593Smuzhiyun FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
39*4882a593Smuzhiyun srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun dtsec_mdio_info.regs =
42*4882a593Smuzhiyun (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Register the 1G MDIO bus */
47*4882a593Smuzhiyun fm_memac_mdio_init(bis, &dtsec_mdio_info);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun tgec_mdio_info.regs =
50*4882a593Smuzhiyun (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
51*4882a593Smuzhiyun tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Register the 10G MDIO bus */
54*4882a593Smuzhiyun fm_memac_mdio_init(bis, &tgec_mdio_info);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Set the two on-board RGMII PHY address */
57*4882a593Smuzhiyun fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
58*4882a593Smuzhiyun fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun switch (srds_s1) {
61*4882a593Smuzhiyun case 0x66:
62*4882a593Smuzhiyun case 0x6b:
63*4882a593Smuzhiyun fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
64*4882a593Smuzhiyun fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
65*4882a593Smuzhiyun fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
66*4882a593Smuzhiyun fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
67*4882a593Smuzhiyun break;
68*4882a593Smuzhiyun default:
69*4882a593Smuzhiyun printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
70*4882a593Smuzhiyun srds_s1);
71*4882a593Smuzhiyun break;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
75*4882a593Smuzhiyun interface = fm_info_get_enet_if(i);
76*4882a593Smuzhiyun switch (interface) {
77*4882a593Smuzhiyun case PHY_INTERFACE_MODE_RGMII:
78*4882a593Smuzhiyun dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
79*4882a593Smuzhiyun fm_info_set_mdio(i, dev);
80*4882a593Smuzhiyun break;
81*4882a593Smuzhiyun default:
82*4882a593Smuzhiyun break;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
87*4882a593Smuzhiyun switch (fm_info_get_enet_if(i)) {
88*4882a593Smuzhiyun case PHY_INTERFACE_MODE_XGMII:
89*4882a593Smuzhiyun dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
90*4882a593Smuzhiyun fm_info_set_mdio(i, dev);
91*4882a593Smuzhiyun break;
92*4882a593Smuzhiyun default:
93*4882a593Smuzhiyun break;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun cpu_eth_init(bis);
98*4882a593Smuzhiyun #endif /* CONFIG_FMAN_ENET */
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return pci_eth_init(bis);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
fdt_fixup_board_enet(void * fdt)103*4882a593Smuzhiyun void fdt_fixup_board_enet(void *fdt)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun return;
106*4882a593Smuzhiyun }
107