1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * CPLD register set of T2080RDB board-specific. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun struct cpld_data { 11*4882a593Smuzhiyun u8 chip_id1; /* 0x00 - Chip ID1 register */ 12*4882a593Smuzhiyun u8 chip_id2; /* 0x01 - Chip ID2 register */ 13*4882a593Smuzhiyun u8 hw_ver; /* 0x02 - Hardware Revision Register */ 14*4882a593Smuzhiyun u8 sw_ver; /* 0x03 - Software Revision register */ 15*4882a593Smuzhiyun u8 res0[12]; /* 0x04 - 0x0F - not used */ 16*4882a593Smuzhiyun u8 reset_ctl; /* 0x10 - Reset control Register */ 17*4882a593Smuzhiyun u8 flash_csr; /* 0x11 - Flash control and status register */ 18*4882a593Smuzhiyun u8 thermal_csr; /* 0x12 - Thermal control and status register */ 19*4882a593Smuzhiyun u8 led_csr; /* 0x13 - LED control and status register */ 20*4882a593Smuzhiyun u8 sfp_csr; /* 0x14 - SFP+ control and status register */ 21*4882a593Smuzhiyun u8 misc_csr; /* 0x15 - Misc control and status register */ 22*4882a593Smuzhiyun u8 boot_or; /* 0x16 - Boot config override register */ 23*4882a593Smuzhiyun u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */ 24*4882a593Smuzhiyun u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */ 25*4882a593Smuzhiyun } cpld_data_t; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun u8 cpld_read(unsigned int reg); 28*4882a593Smuzhiyun void cpld_write(unsigned int reg, u8 value); 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) 31*4882a593Smuzhiyun #define CPLD_WRITE(reg, value) \ 32*4882a593Smuzhiyun cpld_write(offsetof(struct cpld_data, reg), value) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* CPLD on IFC */ 35*4882a593Smuzhiyun #define CPLD_LBMAP_MASK 0x3F 36*4882a593Smuzhiyun #define CPLD_BANK_SEL_MASK 0x07 37*4882a593Smuzhiyun #define CPLD_BANK_OVERRIDE 0x40 38*4882a593Smuzhiyun #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 39*4882a593Smuzhiyun #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ 40*4882a593Smuzhiyun #define CPLD_LBMAP_RESET 0xFF 41*4882a593Smuzhiyun #define CPLD_LBMAP_SHIFT 0x03 42*4882a593Smuzhiyun #define CPLD_BOOT_SEL 0x80 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* RSTCON Register */ 45*4882a593Smuzhiyun #define CPLD_RSTCON_EDC_RST 0x04 46