1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Freescale T2080RDB board-specific CPLD controlling supports.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <command.h>
11*4882a593Smuzhiyun #include "cpld.h"
12*4882a593Smuzhiyun
cpld_read(unsigned int reg)13*4882a593Smuzhiyun u8 cpld_read(unsigned int reg)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun void *p = (void *)CONFIG_SYS_CPLD_BASE;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun return in_8(p + reg);
18*4882a593Smuzhiyun }
19*4882a593Smuzhiyun
cpld_write(unsigned int reg,u8 value)20*4882a593Smuzhiyun void cpld_write(unsigned int reg, u8 value)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun void *p = (void *)CONFIG_SYS_CPLD_BASE;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun out_8(p + reg, value);
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Set the boot bank to the alternate bank */
cpld_set_altbank(void)28*4882a593Smuzhiyun void cpld_set_altbank(void)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun u8 reg = CPLD_READ(flash_csr);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
33*4882a593Smuzhiyun CPLD_WRITE(flash_csr, reg);
34*4882a593Smuzhiyun CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Set the boot bank to the default bank */
cpld_set_defbank(void)38*4882a593Smuzhiyun void cpld_set_defbank(void)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun u8 reg = CPLD_READ(flash_csr);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
43*4882a593Smuzhiyun CPLD_WRITE(flash_csr, reg);
44*4882a593Smuzhiyun CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
do_cpld(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])47*4882a593Smuzhiyun int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun int rc = 0;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun if (argc <= 1)
52*4882a593Smuzhiyun return cmd_usage(cmdtp);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun if (strcmp(argv[1], "reset") == 0) {
55*4882a593Smuzhiyun if (strcmp(argv[2], "altbank") == 0)
56*4882a593Smuzhiyun cpld_set_altbank();
57*4882a593Smuzhiyun else
58*4882a593Smuzhiyun cpld_set_defbank();
59*4882a593Smuzhiyun } else {
60*4882a593Smuzhiyun rc = cmd_usage(cmdtp);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return rc;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun U_BOOT_CMD(
67*4882a593Smuzhiyun cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
68*4882a593Smuzhiyun "Reset the board or alternate bank",
69*4882a593Smuzhiyun "reset: reset to default bank\n"
70*4882a593Smuzhiyun "cpld reset altbank: reset to alternate bank\n"
71*4882a593Smuzhiyun );
72