1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DDR_H__ 8*4882a593Smuzhiyun #define __DDR_H__ 9*4882a593Smuzhiyun struct board_specific_parameters { 10*4882a593Smuzhiyun u32 n_ranks; 11*4882a593Smuzhiyun u32 datarate_mhz_high; 12*4882a593Smuzhiyun u32 rank_gb; 13*4882a593Smuzhiyun u32 clk_adjust; 14*4882a593Smuzhiyun u32 wrlvl_start; 15*4882a593Smuzhiyun u32 wrlvl_ctl_2; 16*4882a593Smuzhiyun u32 wrlvl_ctl_3; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * These tables contain all valid speeds we want to override with board 21*4882a593Smuzhiyun * specific parameters. datarate_mhz_high values need to be in ascending order 22*4882a593Smuzhiyun * for each n_ranks group. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun static const struct board_specific_parameters udimm0[] = { 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * memory controller 0 28*4882a593Smuzhiyun * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | 29*4882a593Smuzhiyun * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun {2, 1200, 0, 10, 7, 0x0708090a, 0x0b0c0d09}, 32*4882a593Smuzhiyun {2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a}, 33*4882a593Smuzhiyun {2, 1700, 0, 10, 8, 0x090a0b0c, 0x0e10110c}, 34*4882a593Smuzhiyun {2, 1900, 0, 10, 8, 0x090b0c0f, 0x1012130d}, 35*4882a593Smuzhiyun {2, 2140, 0, 10, 8, 0x090b0c0f, 0x1012130d}, 36*4882a593Smuzhiyun {1, 1200, 0, 10, 7, 0x0808090a, 0x0b0c0c0a}, 37*4882a593Smuzhiyun {1, 1500, 0, 10, 6, 0x07070809, 0x0a0b0b09}, 38*4882a593Smuzhiyun {1, 1600, 0, 10, 8, 0x090b0b0d, 0x0d0e0f0b}, 39*4882a593Smuzhiyun {1, 1700, 0, 8, 8, 0x080a0a0c, 0x0c0d0e0a}, 40*4882a593Smuzhiyun {1, 1900, 0, 10, 8, 0x090a0c0d, 0x0e0f110c}, 41*4882a593Smuzhiyun {1, 2140, 0, 8, 8, 0x090a0b0d, 0x0e0f110b}, 42*4882a593Smuzhiyun {} 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun static const struct board_specific_parameters rdimm0[] = { 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * memory controller 0 48*4882a593Smuzhiyun * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | 49*4882a593Smuzhiyun * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun /* TODO: need tuning these parameters if RDIMM is used */ 52*4882a593Smuzhiyun {4, 1350, 0, 10, 9, 0x08070605, 0x06070806}, 53*4882a593Smuzhiyun {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906}, 54*4882a593Smuzhiyun {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, 55*4882a593Smuzhiyun {2, 1350, 0, 10, 9, 0x08070605, 0x06070806}, 56*4882a593Smuzhiyun {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, 57*4882a593Smuzhiyun {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, 58*4882a593Smuzhiyun {1, 1350, 0, 10, 9, 0x08070605, 0x06070806}, 59*4882a593Smuzhiyun {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, 60*4882a593Smuzhiyun {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07}, 61*4882a593Smuzhiyun {} 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun static const struct board_specific_parameters *udimms[] = { 65*4882a593Smuzhiyun udimm0, 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun static const struct board_specific_parameters *rdimms[] = { 69*4882a593Smuzhiyun rdimm0, 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun #endif 72