1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/fsl_law.h> 9*4882a593Smuzhiyun #include <asm/mmu.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct law_entry law_table[] = { 12*4882a593Smuzhiyun #ifdef CONFIG_MTD_NOR_FLASH 13*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), 14*4882a593Smuzhiyun #endif 15*4882a593Smuzhiyun #ifdef CONFIG_SYS_BMAN_MEM_PHYS 16*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun #ifdef CONFIG_SYS_QMAN_MEM_PHYS 19*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), 20*4882a593Smuzhiyun #endif 21*4882a593Smuzhiyun #ifdef CONFIG_SYS_CPLD_BASE_PHYS 22*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun #ifdef CONFIG_SYS_DCSRBAR_PHYS 25*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), 26*4882a593Smuzhiyun #endif 27*4882a593Smuzhiyun #ifdef CONFIG_SYS_NAND_BASE_PHYS 28*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun int num_law_entries = ARRAY_SIZE(law_table); 33