1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <command.h>
11*4882a593Smuzhiyun #include <fsl_diu_fb.h>
12*4882a593Smuzhiyun #include <linux/ctype.h>
13*4882a593Smuzhiyun #include <video_fb.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "../common/diu_ch7301.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "cpld.h"
18*4882a593Smuzhiyun #include "t104xrdb.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * DIU Area Descriptor
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * Note that we need to byte-swap the value before it's written to the AD
24*4882a593Smuzhiyun * register. So even though the registers don't look like they're in the same
25*4882a593Smuzhiyun * bit positions as they are on the MPC8610, the same value is written to the
26*4882a593Smuzhiyun * AD register on the MPC8610 and on the P1022.
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun #define AD_BYTE_F 0x10000000
29*4882a593Smuzhiyun #define AD_ALPHA_C_SHIFT 25
30*4882a593Smuzhiyun #define AD_BLUE_C_SHIFT 23
31*4882a593Smuzhiyun #define AD_GREEN_C_SHIFT 21
32*4882a593Smuzhiyun #define AD_RED_C_SHIFT 19
33*4882a593Smuzhiyun #define AD_PIXEL_S_SHIFT 16
34*4882a593Smuzhiyun #define AD_COMP_3_SHIFT 12
35*4882a593Smuzhiyun #define AD_COMP_2_SHIFT 8
36*4882a593Smuzhiyun #define AD_COMP_1_SHIFT 4
37*4882a593Smuzhiyun #define AD_COMP_0_SHIFT 0
38*4882a593Smuzhiyun
diu_set_pixel_clock(unsigned int pixclock)39*4882a593Smuzhiyun void diu_set_pixel_clock(unsigned int pixclock)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun unsigned long speed_ccb, temp;
42*4882a593Smuzhiyun u32 pixval;
43*4882a593Smuzhiyun int ret;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun speed_ccb = get_bus_freq(0);
46*4882a593Smuzhiyun temp = 1000000000 / pixclock;
47*4882a593Smuzhiyun temp *= 1000;
48*4882a593Smuzhiyun pixval = speed_ccb / temp;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* Program HDMI encoder */
51*4882a593Smuzhiyun ret = diu_set_dvi_encoder(temp);
52*4882a593Smuzhiyun if (ret) {
53*4882a593Smuzhiyun puts("Failed to set DVI encoder\n");
54*4882a593Smuzhiyun return;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* Program pixel clock */
58*4882a593Smuzhiyun out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
59*4882a593Smuzhiyun ((pixval << PXCK_BITS_START) & PXCK_MASK));
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* enable clock*/
62*4882a593Smuzhiyun out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
63*4882a593Smuzhiyun ((pixval << PXCK_BITS_START) & PXCK_MASK));
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
platform_diu_init(unsigned int xres,unsigned int yres,const char * port)66*4882a593Smuzhiyun int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun u32 pixel_format;
69*4882a593Smuzhiyun u8 sw;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /*Configure Display ouput port as HDMI*/
72*4882a593Smuzhiyun sw = CPLD_READ(sfp_ctl_status);
73*4882a593Smuzhiyun CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
76*4882a593Smuzhiyun (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
77*4882a593Smuzhiyun (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
78*4882a593Smuzhiyun (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
79*4882a593Smuzhiyun (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun printf("DIU: Switching to monitor DVI @ %ux%u\n", xres, yres);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return fsl_diu_init(xres, yres, pixel_format, 0);
84*4882a593Smuzhiyun }
85