1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DDR_H__ 8*4882a593Smuzhiyun #define __DDR_H__ 9*4882a593Smuzhiyun struct board_specific_parameters { 10*4882a593Smuzhiyun u32 n_ranks; 11*4882a593Smuzhiyun u32 datarate_mhz_high; 12*4882a593Smuzhiyun u32 rank_gb; 13*4882a593Smuzhiyun u32 clk_adjust; 14*4882a593Smuzhiyun u32 wrlvl_start; 15*4882a593Smuzhiyun u32 wrlvl_ctl_2; 16*4882a593Smuzhiyun u32 wrlvl_ctl_3; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * These tables contain all valid speeds we want to override with board 21*4882a593Smuzhiyun * specific parameters. datarate_mhz_high values need to be in ascending order 22*4882a593Smuzhiyun * for each n_ranks group. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun static const struct board_specific_parameters udimm0[] = { 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * memory controller 0 28*4882a593Smuzhiyun * num| hi| rank| clk| wrlvl | wrlvl 29*4882a593Smuzhiyun * ranks| mhz| GB |adjst| start | ctl2 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_DDR4 32*4882a593Smuzhiyun {2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a}, 33*4882a593Smuzhiyun #elif defined(CONFIG_SYS_FSL_DDR3) 34*4882a593Smuzhiyun {2, 833, 4, 8, 6, 0x06060607, 0x08080807}, 35*4882a593Smuzhiyun {2, 833, 0, 8, 6, 0x06060607, 0x08080807}, 36*4882a593Smuzhiyun {2, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, 37*4882a593Smuzhiyun {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, 38*4882a593Smuzhiyun {2, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, 39*4882a593Smuzhiyun {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, 40*4882a593Smuzhiyun {1, 833, 4, 8, 6, 0x06060607, 0x08080807}, 41*4882a593Smuzhiyun {1, 833, 0, 8, 6, 0x06060607, 0x08080807}, 42*4882a593Smuzhiyun {1, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, 43*4882a593Smuzhiyun {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, 44*4882a593Smuzhiyun {1, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, 45*4882a593Smuzhiyun {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, 46*4882a593Smuzhiyun #else 47*4882a593Smuzhiyun #error DDR type not defined 48*4882a593Smuzhiyun #endif 49*4882a593Smuzhiyun {} 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #endif 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun static const struct board_specific_parameters *udimms[] = { 55*4882a593Smuzhiyun udimm0, 56*4882a593Smuzhiyun }; 57