1*4882a593Smuzhiyun /** 2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file provides support for the ngPIXIS, a board-specific FPGA used on 7*4882a593Smuzhiyun * some Freescale reference boards. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * CPLD register set. Feel free to add board-specific #ifdefs where necessary. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun struct cpld_data { 14*4882a593Smuzhiyun u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ 15*4882a593Smuzhiyun u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ 16*4882a593Smuzhiyun u8 hw_ver; /* 0x02 - Hardware Revision Register */ 17*4882a593Smuzhiyun u8 sw_ver; /* 0x03 - Software Revision register */ 18*4882a593Smuzhiyun u8 res0[12]; /* 0x04 - 0x0F - not used */ 19*4882a593Smuzhiyun u8 reset_ctl1; /* 0x10 - Reset control Register1 */ 20*4882a593Smuzhiyun u8 reset_ctl2; /* 0x11 - Reset control Register2 */ 21*4882a593Smuzhiyun u8 int_status; /* 0x12 - Interrupt status Register */ 22*4882a593Smuzhiyun u8 flash_ctl_status; /* 0x13 - Flash control and status register */ 23*4882a593Smuzhiyun u8 fan_ctl_status; /* 0x14 - Fan control and status register */ 24*4882a593Smuzhiyun #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 25*4882a593Smuzhiyun u8 int_mask; /* 0x15 - Interrupt mask Register */ 26*4882a593Smuzhiyun #else 27*4882a593Smuzhiyun u8 led_ctl_status; /* 0x15 - LED control and status register */ 28*4882a593Smuzhiyun #endif 29*4882a593Smuzhiyun u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ 30*4882a593Smuzhiyun u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ 31*4882a593Smuzhiyun u8 boot_override; /* 0x18 - Boot override register */ 32*4882a593Smuzhiyun u8 boot_config1; /* 0x19 - Boot config override register*/ 33*4882a593Smuzhiyun u8 boot_config2; /* 0x1A - Boot config override register*/ 34*4882a593Smuzhiyun } cpld_data_t; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Pointer to the CPLD register set */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun u8 cpld_read(unsigned int reg); 40*4882a593Smuzhiyun void cpld_write(unsigned int reg, u8 value); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) 43*4882a593Smuzhiyun #define CPLD_WRITE(reg, value)\ 44*4882a593Smuzhiyun cpld_write(offsetof(struct cpld_data, reg), value) 45*4882a593Smuzhiyun #define MISC_CTL_SG_SEL 0x80 46*4882a593Smuzhiyun #define MISC_CTL_AURORA_SEL 0x02 47*4882a593Smuzhiyun #define MISC_MUX_QE_TDM 0xc0 48