1*4882a593Smuzhiyun /**
2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file provides support for the board-specific CPLD used on some Freescale
7*4882a593Smuzhiyun * reference boards.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * The following macros need to be defined:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <common.h>
15*4882a593Smuzhiyun #include <command.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "cpld.h"
19*4882a593Smuzhiyun
cpld_read(unsigned int reg)20*4882a593Smuzhiyun u8 cpld_read(unsigned int reg)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun void *p = (void *)CONFIG_SYS_CPLD_BASE;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun return in_8(p + reg);
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
cpld_write(unsigned int reg,u8 value)27*4882a593Smuzhiyun void cpld_write(unsigned int reg, u8 value)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun void *p = (void *)CONFIG_SYS_CPLD_BASE;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun out_8(p + reg, value);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /**
35*4882a593Smuzhiyun * Set the boot bank to the alternate bank
36*4882a593Smuzhiyun */
cpld_set_altbank(void)37*4882a593Smuzhiyun void cpld_set_altbank(void)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun u8 reg = CPLD_READ(flash_ctl_status);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun CPLD_WRITE(flash_ctl_status, reg);
44*4882a593Smuzhiyun CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /**
48*4882a593Smuzhiyun * Set the boot bank to the default bank
49*4882a593Smuzhiyun */
cpld_set_defbank(void)50*4882a593Smuzhiyun void cpld_set_defbank(void)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun u8 reg = CPLD_READ(flash_ctl_status);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun CPLD_WRITE(flash_ctl_status, reg);
57*4882a593Smuzhiyun CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #ifdef DEBUG
cpld_dump_regs(void)61*4882a593Smuzhiyun static void cpld_dump_regs(void)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
64*4882a593Smuzhiyun printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
65*4882a593Smuzhiyun printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
66*4882a593Smuzhiyun printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
67*4882a593Smuzhiyun printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
68*4882a593Smuzhiyun printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
69*4882a593Smuzhiyun printf("int_status = 0x%02x\n", CPLD_READ(int_status));
70*4882a593Smuzhiyun printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
71*4882a593Smuzhiyun printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
72*4882a593Smuzhiyun #if defined(CONFIG_TARGET_T1040D4D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
73*4882a593Smuzhiyun printf("int_mask = 0x%02x\n", CPLD_READ(int_mask));
74*4882a593Smuzhiyun #else
75*4882a593Smuzhiyun printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
76*4882a593Smuzhiyun #endif
77*4882a593Smuzhiyun printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
78*4882a593Smuzhiyun printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
79*4882a593Smuzhiyun printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
80*4882a593Smuzhiyun printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
81*4882a593Smuzhiyun printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
82*4882a593Smuzhiyun putc('\n');
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun #endif
85*4882a593Smuzhiyun
do_cpld(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])86*4882a593Smuzhiyun int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun int rc = 0;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun if (argc <= 1)
91*4882a593Smuzhiyun return cmd_usage(cmdtp);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun if (strcmp(argv[1], "reset") == 0) {
94*4882a593Smuzhiyun if (strcmp(argv[2], "altbank") == 0)
95*4882a593Smuzhiyun cpld_set_altbank();
96*4882a593Smuzhiyun else
97*4882a593Smuzhiyun cpld_set_defbank();
98*4882a593Smuzhiyun #ifdef DEBUG
99*4882a593Smuzhiyun } else if (strcmp(argv[1], "dump") == 0) {
100*4882a593Smuzhiyun cpld_dump_regs();
101*4882a593Smuzhiyun #endif
102*4882a593Smuzhiyun } else
103*4882a593Smuzhiyun rc = cmd_usage(cmdtp);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return rc;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun U_BOOT_CMD(
109*4882a593Smuzhiyun cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
110*4882a593Smuzhiyun "Reset the board or alternate bank",
111*4882a593Smuzhiyun "reset - hard reset to default bank\n"
112*4882a593Smuzhiyun "cpld reset altbank - reset to alternate bank\n"
113*4882a593Smuzhiyun #ifdef DEBUG
114*4882a593Smuzhiyun "cpld dump - display the CPLD registers\n"
115*4882a593Smuzhiyun #endif
116*4882a593Smuzhiyun );
117