1*4882a593Smuzhiyun#PBL preamble and RCW header for T1023RDB 2*4882a593Smuzhiyunaa55aa55 010e0100 3*4882a593Smuzhiyun#SerDes Protocol: 0x77 4*4882a593Smuzhiyun#Default Core=1200MHz, DDR=1600MT/s with single source clock 5*4882a593Smuzhiyun0810000c 00000000 00000000 00000000 6*4882a593Smuzhiyun3b800003 00000012 e8104000 21000000 7*4882a593Smuzhiyun00000000 00000000 00000000 00022800 8*4882a593Smuzhiyun00000130 04020200 00000000 00000006 9