1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __T1024QDS_QIXIS_H__ 8*4882a593Smuzhiyun #define __T1024QDS_QIXIS_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Definitions of QIXIS Registers for T1024/T1023 QDS */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ 13*4882a593Smuzhiyun #define BRDCFG4_EMISEL_MASK 0xE0 14*4882a593Smuzhiyun #define BRDCFG4_EMISEL_SHIFT 5 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/ 17*4882a593Smuzhiyun #define BRDCFG5_IMX_MASK 0xC0 18*4882a593Smuzhiyun #define BRDCFG5_IMX_DIU 0x80 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define BRDCFG5_SPIRTE_MASK 0x07 21*4882a593Smuzhiyun #define BRDCFG5_SPIRTE_TDM 0x01 22*4882a593Smuzhiyun #define BRDCFG5_SPIRTE_SDHC 0x02 23*4882a593Smuzhiyun #define BRDCFG9_XFI_TX_DISABLE 0x10 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* BRDCFG13[0:5] TDM configuration and setup */ 26*4882a593Smuzhiyun #define BRDCFG13_TDM_MASK 0xfc 27*4882a593Smuzhiyun #define BRDCFG13_TDM_INTERFACE 0x37 28*4882a593Smuzhiyun #define BRDCFG13_HDLC_LOOPBACK 0x29 29*4882a593Smuzhiyun #define BRDCFG13_TDM_LOOPBACK 0x31 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* BRDCFG15[3] controls LCD Panel Powerdown */ 32*4882a593Smuzhiyun #define BRDCFG15_LCDFM 0x20 33*4882a593Smuzhiyun #define BRDCFG15_LCDPD 0x10 34*4882a593Smuzhiyun #define BRDCFG15_LCDPD_MASK 0x10 35*4882a593Smuzhiyun #define BRDCFG15_LCDPD_ENABLED 0x00 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* BRDCFG15[6:7] controls DIU MUX selction*/ 38*4882a593Smuzhiyun #define BRDCFG15_DIUSEL_MASK 0x03 39*4882a593Smuzhiyun #define BRDCFG15_DIUSEL_HDMI 0x00 40*4882a593Smuzhiyun #define BRDCFG15_DIUSEL_LCD 0x01 41*4882a593Smuzhiyun #define BRDCFG15_DIUSEL_UCC 0x02 42*4882a593Smuzhiyun #define BRDCFG15_DIUSEL_TDM 0x03 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* SYSCLK */ 45*4882a593Smuzhiyun #define QIXIS_SYSCLK_66 0x0 46*4882a593Smuzhiyun #define QIXIS_SYSCLK_83 0x1 47*4882a593Smuzhiyun #define QIXIS_SYSCLK_100 0x2 48*4882a593Smuzhiyun #define QIXIS_SYSCLK_125 0x3 49*4882a593Smuzhiyun #define QIXIS_SYSCLK_133 0x4 50*4882a593Smuzhiyun #define QIXIS_SYSCLK_150 0x5 51*4882a593Smuzhiyun #define QIXIS_SYSCLK_160 0x6 52*4882a593Smuzhiyun #define QIXIS_SYSCLK_166 0x7 53*4882a593Smuzhiyun #define QIXIS_SYSCLK_64 0x8 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* DDRCLK */ 56*4882a593Smuzhiyun #define QIXIS_DDRCLK_66 0x0 57*4882a593Smuzhiyun #define QIXIS_DDRCLK_100 0x1 58*4882a593Smuzhiyun #define QIXIS_DDRCLK_125 0x2 59*4882a593Smuzhiyun #define QIXIS_DDRCLK_133 0x3 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define QIXIS_SRDS1CLK_122 0x5a 63*4882a593Smuzhiyun #define QIXIS_SRDS1CLK_125 0x5e 64*4882a593Smuzhiyun #endif 65